[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[MiNT] Patch: Firebee onboard Ethernet driver
Hello,
here's the driver for Firebee Ethernet support under Freemint.
sys_cookie.h.patch, message: Added definition for FireTOS DMA API
sys_sockets_xif_fec.patch, message: Added support for FireBee onboard
Ethernet Controller
Large parts of the driver (DMA interface) can be probably put into some
directory like sys/arch/firebee - however, I leave that as an todo when
another DMA driver arives. :)
Alan, please commit or reject ;)
Greets,
m
diff -aurN -x CVS ./xif.orig//fec/am79c874.c ./xif/fec/am79c874.c
--- ./xif.orig//fec/am79c874.c 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/am79c874.c 2011-10-31 00:35:01.000000000 +0100
@@ -0,0 +1,113 @@
+
+#include "buf.h"
+#include "inet4/if.h"
+#include "inet4/ifeth.h"
+#include "netinfo.h"
+#include "mint/sockio.h"
+
+
+
+#include "platform/board.h"
+#include "fec.h"
+#include "am79c874.h"
+
+
+
+/********************************************************************/
+/* Initialize the AM79C874 PHY
+ *
+ * This function sets up the Auto-Negotiate Advertisement register
+ * within the PHY and then forces the PHY to auto-negotiate for
+ * it's settings.
+ *
+ * Params:
+ * fec_ch FEC channel
+ * phy_addr Address of the PHY.
+ * speed Desired speed (10BaseT or 100BaseTX)
+ * duplex Desired duplex (Full or Half)
+
+ * Return Value:
+ * 0 if MII commands fail
+ * 1 otherwise
+ */
+long am79c874_init(uint8 fec_ch, uint8 phy_addr, uint8 speed, uint8 duplex)
+{
+ long timeout;
+ uint16 settings;
+
+ duplex = duplex;
+
+ /* Initialize the MII interface */
+ fec_mii_init(fec_ch, SYSTEM_CLOCK);
+ /* Reset the PHY */
+ if(!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_RESET))
+ {
+ KDEBUG(("PHY error reset"));
+ return 0;
+ }
+
+ /* Wait for the PHY to reset */
+ for(timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+ {
+ fec_mii_read(fec_ch, phy_addr, MII_AM79C874_CR, &settings);
+ if(!(settings & MII_AM79C874_CR_RESET))
+ break;
+ }
+ if(timeout >= FEC_MII_TIMEOUT)
+ {
+ KDEBUG(("PHY error reset timeout"));
+ return 0;
+ }
+
+ if( speed != FEC_MII_10BASE_T ){
+ KDEBUG(("PHY Enable Auto-Negotiation"));
+ /* Enable Auto-Negotiation */
+ if(!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_AUTON | MII_AM79C874_CR_RST_NEG))
+ {
+ KDEBUG(("PHY error enable Auto-Negotiation"));
+ return 0;
+ }
+ KDEBUG(("PHY Wait for auto-negotiation to complete"));
+ /* Wait for auto-negotiation to complete */
+ for(timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+ {
+ settings = 0;
+ fec_mii_read(fec_ch, phy_addr, MII_AM79C874_SR, &settings);
+ if((settings & AUTONEGLINK) == AUTONEGLINK)
+ break;
+ }
+ if(timeout >= FEC_MII_TIMEOUT)
+ {
+
+ /* Set the default mode (Full duplex, 100 Mbps) */
+ if(!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX))
+ {
+ KDEBUG(("PHY error set default moden"));
+ return 0;
+ }
+ }
+ } else {
+ if(!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, 0))
+ {
+ KDEBUG(("PHY error set force mode"));
+ return 0;
+ }
+ }
+ settings = 0;
+ fec_mii_read(fec_ch, phy_addr, MII_AM79C874_DR, &settings);
+ KDEBUG(("PHY Mode: "));
+ if(settings & MII_AM79C874_DR_DATA_RATE)
+ KDEBUG(("100Mbps "));
+ else
+ KDEBUG(("10Mbps "));
+ if(settings & MII_AM79C874_DR_DPLX)
+ KDEBUG(("Full-duplex"));
+ else
+ KDEBUG(("Half-duplex"));
+ return 1;
+}
+/********************************************************************/
+
+
+
+
diff -aurN -x CVS ./xif.orig//fec/am79c874.h ./xif/fec/am79c874.h
--- ./xif.orig//fec/am79c874.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/am79c874.h 2011-10-11 20:57:26.000000000 +0200
@@ -0,0 +1,87 @@
+/*
+ * File: am79c874.h
+ * Purpose: Driver for the AM79C874 10/100 Ethernet PHY
+ *
+ * Notes:
+ */
+
+#ifndef _AM79C874_H_
+#define _AM79C874_H_
+
+/********************************************************************/
+
+long am79c874_init(uint8 fec_ch, uint8 phy_addr, uint8 speed, uint8 duplex);
+
+/********************************************************************/
+
+/* MII Register Addresses */
+#define MII_AM79C874_CR 0 /* MII Management Control Register */
+#define MII_AM79C874_SR 1 /* MII Management Status Register */
+#define MII_AM79C874_PHYIDR1 2 /* PHY Identifier 1 Register */
+#define MII_AM79C874_PHYIDR2 3 /* PHY Identifier 2 Register */
+#define MII_AM79C874_ANAR 4 /* Auto-Negociation Advertissement Register */
+#define MII_AM79C874_ANLPAR 5 /* Auto-Negociation Link Partner Register */
+#define MII_AM79C874_ANER 6 /* Auto-Negociation Expansion Register */
+#define MII_AM79C874_ANNPTR 7 /* Next Page Advertisement Register */
+#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
+#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
+#define MII_AM79C874_DR 18 /* Diagnostic Register */
+#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
+#define MII_AM79C874_MCR 21 /* ModeControl Register */
+#define MII_AM79C874_DC 23 /* Disconnect Counter */
+#define MII_AM79C874_REC 24 /* Recieve Error Counter */
+
+/* Bit definitions and macros for MII_AM79C874_CR */
+#define MII_AM79C874_CR_RESET (0x8000)
+#define MII_AM79C874_CR_LOOP (0x4000)
+#define MII_AM79C874_CR_100MB (0x2000)
+#define MII_AM79C874_CR_AUTON (0x1000)
+#define MII_AM79C874_CR_POWD (0x0800)
+#define MII_AM79C874_CR_ISO (0x0400)
+#define MII_AM79C874_CR_RST_NEG (0x0200)
+#define MII_AM79C874_CR_DPLX (0x0100)
+#define MII_AM79C874_CR_COL_TST (0x0080)
+#define MII_AM79C874_CR_SPEED_MASK (0x2040)
+#define MII_AM79C874_CR_1000_MPS (0x0040)
+#define MII_AM79C874_CR_100_MPS (0x2000)
+#define MII_AM79C874_CR_10_MPS (0x0000)
+
+/* Bit definitions and macros for MII_AM79C874_SR */
+#define MII_AM79C874_SR_100T4 (0x8000)
+#define MII_AM79C874_SR_100TXF (0x4000)
+#define MII_AM79C874_SR_100TXH (0x2000)
+#define MII_AM79C874_SR_10TF (0x1000)
+#define MII_AM79C874_SR_10TH (0x0800)
+#define MII_AM79C874_SR_PRE_SUP (0x0040)
+#define MII_AM79C874_SR_AUTN_COMP (0x0020)
+#define MII_AM79C874_SR_RF (0x0010)
+#define MII_AM79C874_SR_AUTN_ABLE (0x0008)
+#define MII_AM79C874_SR_LS (0x0004)
+#define MII_AM79C874_SR_JD (0x0002)
+#define MII_AM79C874_SR_EXT (0x0001)
+
+/* Bit definitions and macros for MII_AM79C874_ANLPAR */
+#define MII_AM79C874_ANLPAR_NP (0x8000)
+#define MII_AM79C874_ANLPAR_ACK (0x4000)
+#define MII_AM79C874_ANLPAR_RF (0x2000)
+#define MII_AM79C874_ANLPAR_T4 (0x0200)
+#define MII_AM79C874_ANLPAR_TXFD (0x0100)
+#define MII_AM79C874_ANLPAR_TX (0x0080)
+#define MII_AM79C874_ANLPAR_10FD (0x0040)
+#define MII_AM79C874_ANLPAR_10 (0x0020)
+#define MII_AM79C874_ANLPAR_100 (0x0380)
+#define MII_AM79C874_ANLPAR_PSB_MASK (0x001F)
+#define MII_AM79C874_ANLPAR_PSB_802_3 (0x0001)
+#define MII_AM79C874_ANLPAR_PSB_802_9 (0x0002)
+
+/* Bit definitions and macros for MII_AM79C874_DR */
+#define MII_AM79C874_DR_DPLX (0x0800)
+#define MII_AM79C874_DR_DATA_RATE (0x0400)
+#define MII_AM79C874_DR_RX_PASS (0x0200)
+#define MII_AM79C874_DR_RX_LOCK (0x0100)
+
+#define AUTONEGLINK (MII_AM79C874_SR_AUTN_COMP | MII_AM79C874_SR_LS)
+
+/********************************************************************/
+
+#endif /* _AM79C874_H_ */
diff -aurN -x CVS ./xif.orig//fec/BINFILES ./xif/fec/BINFILES
--- ./xif.orig//fec/BINFILES 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/BINFILES 2011-11-08 00:14:36.000000000 +0100
@@ -0,0 +1,5 @@
+# This file gets included by the Makefile in this directory to determine
+# the files that should go only into binary distributions.
+
+BINFILES = \
+ fec.xif
diff -aurN -x CVS ./xif.orig//fec/dma.c ./xif/fec/dma.c
--- ./xif.orig//fec/dma.c 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/dma.c 2011-11-10 21:03:49.000000000 +0100
@@ -0,0 +1,31 @@
+#include "global.h"
+
+#include "platform/board.h"
+#include "cookie.h"
+
+DMACF_COOKIE * dmac = NULL;
+
+DMACF_COOKIE * mc_dma_init( void )
+{
+ if( dmac != NULL ){
+ return( dmac );
+ }
+
+ struct cookie *cookie = *CJAR;
+ if (cookie)
+ {
+ while (cookie->tag)
+ {
+ if (cookie->tag == COOKIE_DMAC ){
+ dmac = (DMACF_COOKIE*)cookie->value;
+ if( dmac->magic != COOKIE_DMAC ){
+ dmac = NULL;
+ }
+ break;
+ }
+ cookie++;
+ }
+ }
+ return( dmac );
+}
+
diff -aurN -x CVS ./xif.orig//fec/EXTRAFILES ./xif/fec/EXTRAFILES
--- ./xif.orig//fec/EXTRAFILES 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/EXTRAFILES 2011-11-08 00:15:28.000000000 +0100
@@ -0,0 +1,4 @@
+# This file gets included by the Makefile in this directory to determine
+# the files that should go only into source distributions.
+
+SRCFILES += BINFILES EXTRAFILES MISCFILES Makefile SRCFILES
diff -aurN -x CVS ./xif.orig//fec/fec.c ./xif/fec/fec.c
--- ./xif.orig//fec/fec.c 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/fec.c 2011-11-10 22:38:41.000000000 +0100
@@ -0,0 +1,1469 @@
+/*
+ * Ethernet driver for Coldfire based Firebee board.
+ * This driver uses the DMA API provided with FireTOS.
+ */
+
+
+#include <osbind.h>
+
+#include "global.h"
+#include "buf.h"
+#include "inet4/if.h"
+#include "inet4/ifeth.h"
+#include "netinfo.h"
+#include "mint/proc.h"
+#include "mint/sockio.h"
+#include "mint/arch/asm_spl.h" // for spl7() locking
+#include "mint/ssystem.h"
+#include "mint/ktypes.h"
+#include "ssystem.h"
+#include "arch/cpu.h" // for cpushi (cache control)
+#include "util.h"
+
+#include "platform/board.h"
+#include "platform/dma.h"
+
+#include "fec.h"
+#include "am79c874.h"
+
+
+#ifndef MAX
+#define MAX(a,b) ((a)>(b)?(a):(b))
+#endif
+
+#ifndef MIN
+#define MIN(a,b) ((a)>(b)?(a):(b))
+#endif
+
+#define ETH_CRC_LEN (4)
+#define ETH_MAX_FRM (ETH_HLEN + ETH_MAX_DLEN + ETH_CRC_LEN)
+#define ETH_MIN_FRM (ETH_HLEN + ETH_MIN_DLEN + ETH_CRC_LEN)
+#define ETH_MTU (ETH_HLEN + ETH_MAX_DLEN)
+
+/* ------------------------ Type definitions ------------------------------ */
+typedef struct s_fec_if_priv
+{
+ struct netif *nif; /* network interface */
+ uint8 ch; /* FEC channel (device) */
+ int8 rx_dma_ch; /* DMA channel */
+ int8 tx_dma_ch; /* DMA channel */
+ TIMEOUT * rx_tout_magic; /* root timeoute id */
+ uint8 mode; /* for promisc mode */
+ uint8 rx_bd_idx; /* circular index into next next buffer desc. to recv. */
+ uint8 tx_bd_idx_next; /* circular index into next buffer desc. to transmit */
+ uint8 tx_bd_idx_cur; /* circular index into next tx buffer desc. to commit */
+ MCD_bufDescFec *rx_bd; /* Receive Buffer Descriptors */
+ MCD_bufDescFec *tx_bd; /* Transmit Buffer Descriptors */
+ uint8 *tx_buf_unaligned[NUM_TXBDS]; /* unaligned buffers to free on close */
+ uint8 *rx_buf_unaligned[NUM_RXBDS];
+} fec_if_t;
+
+
+/* ------------------------ Static variables ------------------------------ */
+/*
+ * interface structures
+ */
+static struct netif if_fec[1];
+static fec_if_t fecif_g[1];
+MCD_bufDescFec *sram_unaligned_bds = (MCD_bufDescFec*)(__MBAR+0x13000);
+
+/* ------------------------ Function declarations ------------------------- */
+long driver_init (void);
+void dbghex( char *, unsigned long val );
+static uint8 fec_hash_address(const uint8 *addr);
+static void fec_set_address(uint8 ch, const uint8 *pa);
+static void fec_reg_dump( uint8 ch );
+static void fec0_rx_timeout(struct proc *, long int arg);
+static void fec0_rx_frame(void);
+static void fec0_tx_frame(void);
+static void fec_tx_frame(struct netif * nif);
+static void fec_rx_timeout(struct netif * nif);
+static void fec_rx_frame(struct netif * nif);
+static void fec_rx_stop(fec_if_t *fec);
+static void fec_tx_stop(fec_if_t *fec);
+static inline int fec_buf_init(fec_if_t *fec);
+
+static void inline fec_buf_flush(fec_if_t *fec);
+static inline MCD_bufDescFec * fec_rx_alloc(fec_if_t *fec);
+static inline MCD_bufDescFec * fec_tx_alloc(fec_if_t *fec);
+static inline MCD_bufDescFec * fec_tx_free(fec_if_t *fec);
+
+
+/*
+ * Prototypes for our service functions
+ */
+static long fec_open (struct netif *);
+static long fec_close (struct netif *);
+static long fec_output (struct netif *, BUF *, const char *, short, short);
+static long fec_ioctl (struct netif *, short, long);
+static long fec_config (struct netif *, struct ifopt *);
+
+unsigned char *board_get_ethaddr(unsigned char *ethaddr);
+unsigned char *board_get_client(unsigned char *client);
+unsigned char *board_get_server(unsigned char *server);
+unsigned char *board_get_gateway(unsigned char *gateway);
+unsigned char *board_get_netmask(unsigned char *netmask);
+
+unsigned char *board_get_ethaddr(unsigned char *ethaddr)
+{
+ int i;
+ for(i = 0; i < 6; i++)
+ ethaddr[i] = ((PARAM *)PARAMS_ADDRESS)->ethaddr[i];
+ return ethaddr;
+}
+
+unsigned char *board_get_client(unsigned char *client)
+{
+ int i;
+ for(i = 0; i < 4; i++)
+ client[i] = ((PARAM *)PARAMS_ADDRESS)->client[i];
+ return client;
+}
+
+unsigned char *board_get_server(unsigned char *server)
+{
+ int i;
+ for(i = 0; i < 4; i++)
+ server[i] = ((PARAM *)PARAMS_ADDRESS)->server[i];
+ return server;
+}
+
+unsigned char *board_get_gateway(unsigned char *gateway)
+{
+ int i;
+ for(i = 0; i < 4; i++)
+ gateway[i] = ((PARAM *)PARAMS_ADDRESS)->gateway[i];
+ return gateway;
+}
+
+unsigned char *board_get_netmask(unsigned char *netmask)
+{
+ int i;
+ for(i = 0; i < 4; i++)
+ netmask[i] = ((PARAM *)PARAMS_ADDRESS)->netmask[i];
+ return netmask;
+}
+
+static char * dbgbuf[128];
+void dbghex( char * str, unsigned long value )
+{
+ ksprintf(
+ (char*)&dbgbuf, "%s:\t0x%04x%04x",
+ str,
+ (short)((value&0xFFFF0000)>>16),
+ (short)(value&0xFFFF)
+ );
+ KDEBUG(( (char*)&dbgbuf ));
+}
+
+
+
+/********************************************************************/
+/*
+ * Write a value to a PHY's MII register.
+ *
+ * Parameters:
+ * ch FEC channel
+ * phy_addr Address of the PHY.
+ * reg_addr Address of the register in the PHY.
+ * data Data to be written to the PHY register.
+ *
+ * Return Values:
+ * 0 on failure
+ * 1 on success.
+ *
+ * Please refer to your PHY manual for registers and their meanings.
+ * mii_write() polls for the FEC's MII interrupt event (which should
+ * be masked from the interrupt handler) and clears it. If after a
+ * suitable amount of time the event isn't triggered, a value of 0
+ * is returned.
+ */
+long
+fec_mii_write(uint8 ch, uint8 phy_addr, uint8 reg_addr, uint16 data)
+{
+ long timeout;
+ uint32 eimr;
+
+ /*
+ * Clear the MII interrupt bit
+ */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII;
+
+ /*
+ * Write to the MII Management Frame Register to kick-off
+ * the MII write
+ */
+ MCF_FEC_MMFR(ch) = 0
+ | MCF_FEC_MMFR_ST_01
+ | MCF_FEC_MMFR_OP_WRITE
+ | MCF_FEC_MMFR_PA((uint32)phy_addr)
+ | MCF_FEC_MMFR_RA((uint32)reg_addr)
+ | MCF_FEC_MMFR_TA_10
+ | MCF_FEC_MMFR_DATA(data);
+
+ /*
+ * Mask the MII interrupt
+ */
+ eimr = MCF_FEC_EIMR(ch);
+ MCF_FEC_EIMR(ch) &= ~MCF_FEC_EIMR_MII;
+
+ /*
+ * Poll for the MII interrupt (interrupt should be masked)
+ */
+ for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+ {
+ if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII)
+ break;
+ }
+ if(timeout == FEC_MII_TIMEOUT)
+ {
+ KDEBUG(("fec_mii_write failed!"));
+ return 0;
+ }
+
+ /*
+ * Clear the MII interrupt bit
+ */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII;
+
+ /*
+ * Restore the EIMR
+ */
+ MCF_FEC_EIMR(ch) = eimr;
+
+ return 1;
+}
+/********************************************************************/
+/*
+ * Read a value from a PHY's MII register.
+ *
+ * Parameters:
+ * ch FEC channel
+ * phy_addr Address of the PHY.
+ * reg_addr Address of the register in the PHY.
+ * data Pointer to storage for the Data to be read
+ * from the PHY register (passed by reference)
+ *
+ * Return Values:
+ * 0 on failure
+ * 1 on success.
+ *
+ * Please refer to your PHY manual for registers and their meanings.
+ * mii_read() polls for the FEC's MII interrupt event (which should
+ * be masked from the interrupt handler) and clears it. If after a
+ * suitable amount of time the event isn't triggered, a value of 0
+ * is returned.
+ */
+long
+fec_mii_read(uint8 ch, uint8 phy_addr, uint8 reg_addr, uint16 *data)
+{
+ long timeout;
+
+ /*
+ * Clear the MII interrupt bit
+ */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII;
+
+ /*
+ * Write to the MII Management Frame Register to kick-off
+ * the MII read
+ */
+ MCF_FEC_MMFR(ch) = 0
+ | MCF_FEC_MMFR_ST_01
+ | MCF_FEC_MMFR_OP_READ
+ | MCF_FEC_MMFR_PA((uint32)phy_addr)
+ | MCF_FEC_MMFR_RA((uint32)reg_addr)
+ | MCF_FEC_MMFR_TA_10;
+
+ /*
+ * Poll for the MII interrupt (interrupt should be masked)
+ */
+ for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+ {
+ if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII)
+ break;
+ }
+
+ if(timeout == FEC_MII_TIMEOUT)
+ {
+ KDEBUG(("fec_mii_read failed!"));
+ return 0;
+ }
+
+ /*
+ * Clear the MII interrupt bit
+ */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII;
+
+ *data = (uint16)(MCF_FEC_MMFR(ch) & 0x0000FFFF);
+
+ return 1;
+}
+/********************************************************************/
+/*
+ * Initialize the MII interface controller
+ *
+ * Parameters:
+ * ch FEC channel
+ * sys_clk System Clock Frequency (in MHz)
+ */
+void
+fec_mii_init(uint8 ch, uint32 sys_clk)
+{
+
+ /*
+ * Initialize the MII clock (EMDC) frequency
+ *
+ * Desired MII clock is 2.5MHz
+ * MII Speed Setting = System_Clock / (2.5MHz * 2)
+
+ * (plus 1 to make sure we round up)
+ */
+ MCF_FEC_MSCR(ch) = MCF_FEC_MSCR_MII_SPEED((sys_clk/5)+1);
+
+ /*
+ * Make sure the external interface signals are enabled
+ */
+ if (ch == 1)
+ MCF_GPIO_PAR_FECI2CIRQ |= 0
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO;
+ else
+ MCF_GPIO_PAR_FECI2CIRQ |= 0
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO;
+}
+
+/********************************************************************/
+/*
+ * Generate the hash table settings for the given address
+ *
+ * Parameters:
+ * addr 48-bit (6 byte) Address to generate the hash for
+ *
+ * Return Value:
+ * The 6 most significant bits of the 32-bit CRC result
+ */
+static uint8 fec_hash_address(const uint8 *addr)
+{
+ uint32 crc;
+ uint8 byte;
+ int i, j;
+ crc = 0xFFFFFFFF;
+ for(i=0; i<6; ++i)
+ {
+ byte = addr[i];
+ for(j=0; j<8; j++)
+ {
+ if((byte & 0x01)^(crc & 0x01))
+ {
+ crc >>= 1;
+ crc = crc ^ 0xEDB88320;
+ }
+ else
+ crc >>= 1;
+ byte >>= 1;
+ }
+ }
+ return(uint8)(crc >> 26);
+}
+
+/********************************************************************/
+/*
+ * Set the Physical (Hardware) Address and the Individual Address
+ * Hash in the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ * pa Physical (Hardware) Address for the selected FEC
+ */
+static void fec_set_address(uint8 ch, const uint8 *pa)
+{
+ uint8 crc;
+ /* Set the Physical Address */
+ MCF_FEC_PALR(ch) = (uint32)(((uint32)pa[0]<<24) | ((uint32)pa[1]<<16) | (pa[2]<<8) | pa[3]);
+ MCF_FEC_PAUR(ch) = (uint32)(((uint32)pa[4]<<24) | ((uint32)pa[5]<<16));
+ /* Calculate and set the hash for given Physical Address
+ in the Individual Address Hash registers */
+ crc = fec_hash_address(pa);
+ if(crc >= 32)
+ MCF_FEC_IAUR(ch) |= (uint32)(1 << (crc - 32));
+ else
+ MCF_FEC_IALR(ch) |= (uint32)(1 << crc);
+}
+
+
+/********************************************************************/
+/*
+ * Display some of the registers for debugging
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+void
+fec_reg_dump(uint8 ch)
+{
+ if(ch == 0)
+ KDEBUG(("------------- FEC0"));
+ else
+ KDEBUG(("------------- FEC1"));
+
+ dbghex("EIR (Interrupt Event)", MCF_FEC_EIR(ch) );
+ dbghex("EIMR (Interrupt Mask)", MCF_FEC_EIMR(ch) );
+ dbghex("ECR (Ethernet Control)", MCF_FEC_ECR(ch) );
+ dbghex("MMFR (MMFR)", MCF_FEC_MMFR(ch) );
+ dbghex("MSCR (MII Speed Control)", MCF_FEC_MSCR(ch) );
+ dbghex("MIBC (MIB Control/Status)", MCF_FEC_MIBC(ch) );
+ dbghex("RCR (Receive Control)", MCF_FEC_RCR(ch) );
+ dbghex("RHASH (Receive Hash)", MCF_FEC_R_HASH(ch) );
+ dbghex("TCR (Transmit Control)", MCF_FEC_TCR(ch) );
+ dbghex("PALR (Physical Address Low)", MCF_FEC_PALR(ch) );
+ dbghex("PAHR (Physical Address High)", MCF_FEC_PAUR(ch) );
+ dbghex("OPD (Opcode / Pause Duration)", MCF_FEC_OPD(ch) );
+ dbghex("IAUR (Individual Address Upper )", MCF_FEC_IAUR(ch) );
+ dbghex("IALR (Individual Address Lower )", MCF_FEC_IALR(ch) );
+ dbghex("GAUR (Group Address Upper )", MCF_FEC_GAUR(ch) );
+ dbghex("GALR (Group Address Lower)", MCF_FEC_GALR(ch) );
+ dbghex("FECTFWR (Transmit FIFO Watermark)", MCF_FEC_FECTFWR(ch) );
+ dbghex("FECRFSR (Receive FIFO Status)", MCF_FEC_FECRFSR(ch) );
+ dbghex("FECRFCR (Receive FIFO Control)", MCF_FEC_FECRFCR(ch) );
+ dbghex("FECRLRFP (Receive FIFO Last Read Frame Pointer)", MCF_FEC_FECRLRFP(ch) );
+ dbghex("FECRLWFP (Receive FIFO Last Write Frame Pointer)", MCF_FEC_FECRLWFP(ch) );
+ dbghex("FECRFAR (Receive FIFO Alarm)", MCF_FEC_FECRFAR(ch) );
+ dbghex("FECRFRP (Receive FIFO Read Pointer)", MCF_FEC_FECRFRP(ch) );
+ dbghex("FECRFWP (Receive FIFO Write Pointer)", MCF_FEC_FECRFWP(ch));
+ dbghex("FECTFSR (Transmit FIFO Status)", MCF_FEC_FECTFSR(ch));
+ dbghex("FECTFCR (Transmit FIFO Control)", MCF_FEC_FECTFCR(ch));
+ dbghex("FECTLRFP (Transmit FIFO Last Read Frame Pointer)", MCF_FEC_FECTLRFP(ch));
+ dbghex("FECTLWFP (Transmit FIFO Last Write Frame Pointer)", MCF_FEC_FECTLWFP(ch));
+ dbghex("FECTFAR (Transmit FIFO Alarm)", MCF_FEC_FECTFAR(ch));
+ dbghex("FECTFRP (Transmit FIFO Read Pointer)", MCF_FEC_FECTFRP(ch) );
+ dbghex("FECTFWP (Transmit FIFO Write Pointer )", MCF_FEC_FECTFWP(ch) );
+ dbghex("FRST (FIFO Reset Register)", MCF_FEC_FRST(ch) );
+ dbghex("FECCTCWR (CRC and Transmit Frame Control Word )", MCF_FEC_CTCWR(ch) );
+ KDEBUG(("-------------------------------"));
+}
+
+
+/********************************************************************/
+/*
+ * Set the duplex on the selected FEC controller
+ *
+ * Parameters:
+ * ch FEC channel
+ * duplex FEC_MII_FULL_DUPLEX or FEC_MII_HALF_DUPLEX
+ */
+void fec_duplex(uint8 ch, uint8 duplex)
+{
+ switch (duplex)
+ {
+ case FEC_MII_HALF_DUPLEX:
+ MCF_FEC_RCR(ch) |= MCF_FEC_RCR_DRT;
+ MCF_FEC_TCR(ch) &= (uint32)~MCF_FEC_TCR_FDEN;
+ break;
+ case FEC_MII_FULL_DUPLEX:
+ default:
+ MCF_FEC_RCR(ch) &= (uint32)~MCF_FEC_RCR_DRT;
+ MCF_FEC_TCR(ch) |= MCF_FEC_TCR_FDEN;
+ break;
+ }
+}
+
+
+/********************************************************************/
+/*
+ * Reset the selected FEC controller
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_reset(uint8 ch)
+{
+ int i;
+
+ /* Clear any events in the FIFO status registers */
+ MCF_FEC_FECRFSR(ch) = (MCF_FEC_FECRFSR_OF | MCF_FEC_FECRFSR_UF | MCF_FEC_FECRFSR_RXW | MCF_FEC_FECRFSR_FAE | MCF_FEC_FECRFSR_IP);
+ MCF_FEC_FECTFSR(ch) = (MCF_FEC_FECRFSR_OF | MCF_FEC_FECRFSR_UF | MCF_FEC_FECRFSR_RXW | MCF_FEC_FECRFSR_FAE | MCF_FEC_FECRFSR_IP);
+ /* Reset the FIFOs */
+ MCF_FEC_FRST(ch) |= MCF_FEC_FRST_SW_RST | MCF_FEC_FRST_RST_CTL;
+ MCF_FEC_FRST(ch) = 0;
+
+ /* Set the Reset bit and clear the Enable bit */
+ MCF_FEC_ECR(ch) = MCF_FEC_ECR_RESET;
+ /* Wait at least 8 clock cycles */
+ for(i=0; i<10; i++)
+ asm(" nop");
+
+ MCF_FEC_FECTFSR(ch) = (MCF_FEC_FECTFSR(ch) | MCF_FEC_FECTFSR_TXW );
+}
+
+
+/********************************************************************/
+/*
+ * Enable interrupts on the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ * pri Interrupt Priority
+ * lvl Interrupt Level
+ */
+static void fec_irq_enable(uint8 ch, uint8 lvl, uint8 pri)
+{
+ /* Setup the appropriate ICR */
+ if(ch)
+ MCF_INTC_ICR38 = (uint8)(MCF_INTC_ICRn_IP(pri) | MCF_INTC_ICRn_IL(lvl));
+ else
+ MCF_INTC_ICR39 = (uint8)(MCF_INTC_ICRn_IP(pri) | MCF_INTC_ICRn_IL(lvl));
+ /* Clear any pending FEC interrupt events */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL;
+ /* Unmask all FEC interrupts */
+ MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_UNMASK_ALL;
+ /* Unmask the FEC interrupt in the interrupt controller */
+ if(ch)
+ MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38;
+ else
+ MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK39;
+}
+
+/********************************************************************/
+/*
+ * Disable interrupts on the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_irq_disable(uint8 ch)
+{
+ /* Mask all FEC interrupts */
+ MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL;
+ /* Mask the FEC interrupt in the interrupt controller */
+ if(ch)
+ MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38;
+ else
+ MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK39;
+}
+
+/********************************************************************/
+/*
+ * Enable interrupts on the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_enable(uint8 ch)
+{
+ fec_irq_enable(ch, FEC_INTC_LVL, ch ? FEC1_INTC_PRI : FEC0_INTC_PRI);
+ /* Enable the transmit and receive processing */
+ MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN;
+}
+
+
+/********************************************************************/
+/*
+ * Disable interrupts on the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_disable(uint8 ch)
+{
+ /* Mask the FEC interrupt in the interrupt controller */
+ fec_irq_disable(ch);
+ /* Disable the FEC channel */
+ MCF_FEC_ECR(ch) &= ~MCF_FEC_ECR_ETHER_EN;
+}
+
+/********************************************************************/
+/*
+ * Initialize the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ * mode External interface mode (RMII, MII, 7-wire, or internal loopback)
+ * pa Physical (Hardware) Address for the selected FEC
+ */
+static void fec_init( fec_if_t *fec, uint8 mode, uint8 duplex, const uint8 *pa)
+{
+ uint8 ch = fec->ch;
+ /* Enable all the external interface signals */
+ if(mode == FEC_MODE_7WIRE)
+ {
+ if(ch)
+ MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E17;
+ else
+ MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E07;
+ }
+ else if (mode == FEC_MODE_MII)
+ {
+ if(ch)
+ MCF_GPIO_PAR_FECI2CIRQ |= (MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17);
+ else
+ MCF_GPIO_PAR_FECI2CIRQ |= (MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
+ | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07);
+ }
+ /* Clear the Individual and Group Address Hash registers */
+ MCF_FEC_IALR(ch) = 0;
+ MCF_FEC_IAUR(ch) = 0;
+ MCF_FEC_GALR(ch) = 0;
+ MCF_FEC_GAUR(ch) = 0;
+ /* Set the Physical Address for the selected FEC */
+ fec_set_address(ch, pa);
+ /* Mask all FEC interrupts */
+ MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL;
+ /* Clear all FEC interrupt events */
+ MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL;
+ /* Initialize the Receive Control Register */
+ MCF_FEC_RCR(ch) = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM)
+#ifdef FEC_PROMISCUOUS
+ | MCF_FEC_RCR_PROM
+#endif
+ | MCF_FEC_RCR_FCE;
+ if(mode == FEC_MODE_MII)
+ MCF_FEC_RCR(ch) |= MCF_FEC_RCR_MII_MODE;
+ else if(mode == FEC_MODE_LOOPBACK)
+ MCF_FEC_RCR(ch) |= (MCF_FEC_RCR_LOOP | MCF_FEC_RCR_PROM);
+ /* Set the duplex */
+ if(mode == FEC_MODE_LOOPBACK)
+ /* Loopback mode must operate in full-duplex */
+ fec_duplex(ch, FEC_MII_FULL_DUPLEX);
+ else
+ fec_duplex(ch, duplex);
+
+ if( fec->mode & FEC_IMODE_PROMISCUOUS ){
+ MCF_FEC_RCR(ch) |= MCF_FEC_RCR_PROM;
+ }
+
+ /* Set Rx FIFO alarm and granularity */
+ MCF_FEC_FECRFCR(ch) = MCF_FEC_FECRFCR_FRM | MCF_FEC_FECRFCR_RXW_MSK | MCF_FEC_FECRFCR_GR(7);
+ MCF_FEC_FECRFAR(ch) = MCF_FEC_FECRFAR_ALARM(768);
+ /* Set Tx FIFO watermark, alarm and granularity */
+ MCF_FEC_FECTFCR(ch) = MCF_FEC_FECTFCR_FRM | MCF_FEC_FECTFCR_TXW_MSK | MCF_FEC_FECTFCR_GR(7);
+
+ MCF_FEC_FECTFAR(ch) = MCF_FEC_FECTFAR_ALARM(256);
+ MCF_FEC_FECTFWR(ch) = MCF_FEC_FECTFWR_X_WMRK_256;
+
+ /* Enable the transmitter to append the CRC */
+ MCF_FEC_CTCWR(ch) = (uint32)(MCF_FEC_CTCWR_TFCW | MCF_FEC_CTCWR_CRC);
+}
+
+/********************************************************************/
+/*
+ * Start the FEC Rx DMA task
+ *
+ * Parameters:
+ * ch FEC channel
+ * rxbd First Rx buffer descriptor in the chain
+ */
+static void fec_rx_start(struct netif * nif, s8 *rxbd, uint8 pri)
+{
+ fec_if_t *fecif = (fec_if_t *)nif->data;
+ uint8 ch = fecif->ch;
+ uint32 initiator;
+ long result;
+
+ if( dma_get_channel( DMA_FEC_RX(ch) ) != -1 )
+ {
+ fec_rx_stop(fecif);
+ }
+ /* Make the initiator assignment */
+ result = dma_set_initiator(DMA_FEC_RX(ch));
+ /* Grab the initiator number */
+ initiator = dma_get_initiator(DMA_FEC_RX(ch));
+ /* Determine the DMA channel running the task for the selected FEC */
+ fecif->rx_dma_ch = dma_set_channel(DMA_FEC_RX(ch), ch ? NULL : fec0_rx_frame);
+#if RX_BUFFER_SIZE != 2048
+#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation"
+#endif
+ result = MCD_startDma(fecif->rx_dma_ch, (s8*)rxbd, 0, MCF_FEC_FECRFDR_ADDR(ch), 0, RX_BUFFER_SIZE,
+ 0, initiator, (long)pri,
+ (uint32)(MCD_FECRX_DMA | MCD_INTERRUPT | MCD_TT_FLAGS_CW | MCD_TT_FLAGS_RL | MCD_TT_FLAGS_SP),
+ (uint32)(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
+ );
+}
+
+/********************************************************************/
+/*
+ * Continue the Rx DMA task
+ *
+ * This routine is called after the DMA task has halted after
+ * encountering an Rx buffer descriptor that wasn't marked as
+ * ready. There is no harm in calling the DMA continue routine
+ * if the DMA is not halted.
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_rx_continue(uint8 ch)
+{
+ int channel;
+ /* Determine the DMA channel running the task for the selected FEC */
+ channel = dma_get_channel(DMA_FEC_RX(ch));
+ /* Continue/restart the DMA task */
+ if(channel != -1)
+ MCD_continDma(channel);
+}
+
+/********************************************************************/
+/*
+ * Stop all frame receptions on the selected FEC
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_rx_stop(fec_if_t *fec)
+{
+
+ uint32 mask;
+ long channel;
+
+ /* Save off the EIMR value */
+ KDEBUG(("fec_rx_stop"));
+
+ mask = MCF_FEC_EIMR(fec->ch);
+ /* Mask all interrupts */
+ MCF_FEC_EIMR(fec->ch) = 0;
+ /* Determine the DMA channel running the task for the selected FEC */
+ channel = dma_get_channel( DMA_FEC_RX(fec->ch) );
+
+ /* Kill the FEC Tx DMA task */
+ if(channel != -1)
+ MCD_killDma(channel);
+
+ /* Free up the FEC requestor from the software maintained initiator list */
+ dma_free_initiator(DMA_FEC_RX(fec->ch));
+
+ /* Free up the DMA channel */
+ dma_free_channel(DMA_FEC_RX(fec->ch));
+
+ /* Restore the interrupt mask register value */
+ MCF_FEC_EIMR(fec->ch) = mask;
+
+ fec->rx_dma_ch = -1;
+ KDEBUG(("fec_rx_stop done"));
+}
+
+
+
+/********************************************************************/
+static void fec_rx_timeout(struct netif * nif)
+{
+ fec_if_t *fecif = (fec_if_t *)nif->data;
+ uint8 ch = fecif->ch;
+ MCD_bufDescFec *dmaBuf;
+ BUF *b;
+ int keep;
+ int rlen;
+
+ while((dmaBuf = fec_rx_alloc(fecif)) != NULL)
+ {
+ /* Check the Receive Frame Status Word for errors
+ - The L bit should always be set
+ - No undefined bits should be set
+ - The upper 5 bits of the length should be cleared */
+ if(!(dmaBuf->statCtrl & MCD_FEC_END_FRAME) || (dmaBuf->statCtrl & 0x0608) || (dmaBuf->length & 0xF800))
+ keep = FALSE;
+ else if(dmaBuf->statCtrl & RX_BD_ERROR)
+ keep = FALSE;
+ else
+ keep = TRUE;
+ if(keep)
+ {
+ rlen = MIN( ETH_MAX_FRM, dmaBuf->length );
+ b = buf_alloc ( rlen +100, 50, BUF_NORMAL );
+ if(!b)
+ {
+ KDEBUG(("buf_alloc failed!"));
+ nif->in_errors++;
+ }
+ else
+ {
+ b->dend = b->dstart + rlen;
+ memcpy( b->dstart, (void*)dmaBuf->dataPointer, b->dend - b->dstart );
+
+ // Pass packet to upper layers
+ if (nif->bpf)
+ bpf_input (nif, b);
+
+ // enqueue packet
+ if(!if_input(nif, b, 0, eth_remove_hdr(b) ))
+ nif->in_packets++;
+ else
+ nif->in_errors++;
+ }
+ }
+ else
+ {
+ KDEBUG(("drop frame\r\n"));
+ nif->in_errors++;
+ }
+ /* Re-initialize the buffer descriptor and notify DMA API*/
+ dmaBuf->length = RX_BUFFER_SIZE;
+ dmaBuf->statCtrl &= (MCD_FEC_WRAP | MCD_FEC_INTERRUPT);
+ dmaBuf->statCtrl |= MCD_FEC_BUF_READY;
+ fec_rx_continue(ch);
+ }
+ fecif->rx_tout_magic = 0;
+}
+
+/*
+ * Receive Frame interrupt
+ */
+static void fec_rx_frame(struct netif * nif)
+{
+ fec_if_t *fecif = (fec_if_t *)nif->data;
+
+ // when processing the frame directly, I get Access Faults and other
+ // strange stuff. So this just triggers an timeout.
+ // Maybe the reason for the fault is nested interrupts? Dunno.
+ if( fecif->rx_tout_magic == 0 )
+ fecif->rx_tout_magic = addroottimeout(0, fec0_rx_timeout, 1 );
+}
+
+
+/********************************************************************/
+/*
+ * Trasmit Frame interrupt handler - this handler is called when the
+ * DMA FEC Tx task generates an interrupt
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_tx_frame(struct netif * nif)
+{
+ fec_if_t * fi = (fec_if_t *)nif->data;
+ MCD_bufDescFec * dmaBuf;
+
+ dmaBuf = fec_tx_free(fi);
+ if( dmaBuf != NULL )
+ {
+ dmaBuf->length = 0;
+ nif->out_packets++;
+ }
+}
+
+static void fec0_rx_frame(void)
+{
+ fec_rx_frame(&if_fec[0]);
+}
+
+static void fec0_rx_timeout( struct proc * p, long int arg )
+{
+ fec_rx_timeout( &if_fec[0] );
+}
+
+
+
+
+/********************************************************************/
+/*
+ * Start the FEC Tx DMA task
+ *
+ * Parameters:
+ * ch FEC channel
+ * txbd First Tx buffer descriptor in the chain
+ */
+static void fec_tx_start(struct netif * nif, s8 *txbd, uint8 pri)
+{
+ fec_if_t *fecif = (fec_if_t *)nif->data;
+ uint8 ch = fecif->ch;
+ uint32 initiator;
+ long result;
+
+ if( dma_get_channel( DMA_FEC_TX(ch) ) != -1 )
+ {
+ fec_tx_stop(fecif);
+ }
+
+ /* Make the initiator assignment */
+ result = dma_set_initiator(DMA_FEC_TX(ch));
+ /* Grab the initiator number */
+ initiator = dma_get_initiator(DMA_FEC_TX(ch));
+ /* Determine the DMA channel running the task for the selected FEC */
+ fecif->tx_dma_ch = dma_set_channel(DMA_FEC_TX(ch), ch ? NULL : fec0_tx_frame);
+ /* Start the Tx DMA task */
+
+ result = MCD_startDma(fecif->tx_dma_ch, txbd, 0, MCF_FEC_FECTFDR_ADDR(ch), 0, ETH_MTU, 0, initiator, (long)pri,
+ (uint32)(MCD_FECTX_DMA | MCD_INTERRUPT | MCD_TT_FLAGS_CW | MCD_TT_FLAGS_RL | MCD_TT_FLAGS_SP),
+ (uint32)(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
+ );
+}
+
+/********************************************************************/
+/*
+ * Stop all transmissions on the selected FEC and kill the DMA task
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+static void fec_tx_stop(fec_if_t *fec)
+{
+ uint32 mask;
+ long channel;
+
+ fec_reg_dump(fec->ch);
+ /* Save off the EIMR value */
+ mask = MCF_FEC_EIMR(fec->ch);
+ /* Mask all interrupts */
+ MCF_FEC_EIMR(fec->ch) = 0;
+ /* If the Ethernet is still enabled... */
+ if(MCF_FEC_ECR(fec->ch) & MCF_FEC_ECR_ETHER_EN)
+ {
+ /* Issue the Graceful Transmit Stop */
+ MCF_FEC_TCR(fec->ch) |= MCF_FEC_TCR_GTS;
+ /* Wait for the Graceful Stop Complete interrupt */
+ int i = 0;
+ while(!(MCF_FEC_EIR(fec->ch) & MCF_FEC_EIR_GRA) && i < 1000 )
+ {
+ if(!(MCF_FEC_ECR(fec->ch) & MCF_FEC_ECR_ETHER_EN))
+ break;
+ i++;
+ }
+ if( i==1000 )
+ KDEBUG(("Gracefull stop failed!"));
+
+ /* Clear the Graceful Stop Complete interrupt */
+ MCF_FEC_EIR(fec->ch) = MCF_FEC_EIR_GRA;
+ }
+ /* Determine the DMA channel running the task for the selected FEC */
+ channel = dma_get_channel(DMA_FEC_TX(fec->ch));
+
+ /* Kill the FEC Tx DMA task */
+ if(channel != -1)
+ MCD_killDma(channel);
+
+ /* Free up the FEC requestor from the software maintained initiator list */
+ dma_free_initiator(DMA_FEC_TX(fec->ch));
+
+
+ /* Free up the DMA channel */
+ dma_free_channel(DMA_FEC_TX(fec->ch));
+
+ /* Restore the interrupt mask register value */
+ MCF_FEC_EIMR(fec->ch) = mask;
+
+ fec->tx_dma_ch = -1;
+
+ KDEBUG(("fec_tx_stop done"));
+}
+
+/********************************************************************/
+/*
+ * Transmit Frame interrupt handler - this handler is called when the
+ * DMA FEC Tx task generates an interrupt
+ *
+ * Parameters:
+ * ch FEC channel
+ */
+
+static void fec0_tx_frame(void)
+{
+ fec_tx_frame(&if_fec[0]);
+}
+
+/*
+
+*/
+
+static inline int fec_buf_init(fec_if_t *fec)
+{
+ int i;
+ /* set up pointers to some buffer descriptors: */
+ fec->rx_bd = (MCD_bufDescFec *) ALIGN4((unsigned long)sram_unaligned_bds );
+ fec->tx_bd = (MCD_bufDescFec *)((long)fec->rx_bd + (sizeof(MCD_bufDescFec) * NUM_RXBDS));
+
+ /* clear pointers, so they can be cleanly handled on alloc failure: */
+ for( i=0; i<NUM_RXBDS; i++)
+ {
+ fec->rx_buf_unaligned[i] = NULL;
+ }
+ for( i=0; i<NUM_TXBDS; i++)
+ {
+ fec->tx_buf_unaligned[i] = NULL;
+ }
+
+ /* initialise the rx buffer descriptors: */
+ for( i=0; i<NUM_RXBDS; i++)
+ {
+ fec->rx_bd[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
+ fec->rx_bd[i].length = RX_BUFFER_SIZE;
+ fec->rx_buf_unaligned[i] = (uint8 *)dma_alloc(RX_BUFFER_SIZE + 16);
+ if( !fec->rx_buf_unaligned[i] )
+ return( 1 );
+ fec->rx_bd[i].dataPointer = ((uint32)(fec->rx_buf_unaligned[i] + 15) & 0xFFFFFFF0);
+ }
+ /* Set wrap bit on last one: */
+ fec->rx_bd[i-1].statCtrl |= MCD_FEC_WRAP;
+
+ for( i=0; i<NUM_TXBDS; i++)
+ {
+ fec->tx_bd[i].statCtrl = MCD_FEC_INTERRUPT;
+ fec->tx_bd[i].length = 0;
+ fec->tx_buf_unaligned[i] = (uint8 *)dma_alloc(TX_BUFFER_SIZE + 16);
+ if( !fec->tx_buf_unaligned[i] )
+ return(1);
+ fec->tx_bd[i].dataPointer = ((uint32)(fec->tx_buf_unaligned[i] + 15) & 0xFFFFFFF0);
+ }
+ /* Set wrap bit on last one: */
+ fec->tx_bd[i-1].statCtrl |= MCD_FEC_WRAP;
+
+ fec->rx_bd_idx = 0;
+ fec->tx_bd_idx_cur = 0;
+ fec->tx_bd_idx_next = 0;
+ return( 0 );
+}
+
+
+static inline void fec_buf_flush(fec_if_t *fec)
+{
+ int i;
+ for( i=0; i<NUM_RXBDS; i++)
+ {
+ if( fec->rx_buf_unaligned[i] != NULL)
+ {
+ dma_free( fec->rx_buf_unaligned[i] );
+ fec->rx_buf_unaligned[i] = NULL;
+ }
+ }
+ for( i=0; i<NUM_TXBDS; i++)
+ {
+ if( fec->tx_buf_unaligned[i] != NULL)
+ {
+ dma_free(fec->tx_buf_unaligned[i]);
+ fec->tx_buf_unaligned[i] = NULL;
+ }
+ }
+}
+
+static inline MCD_bufDescFec * fec_rx_alloc(fec_if_t *fec)
+{
+ long i = fec->rx_bd_idx;
+ /* bail out if the current rx buffer isn't owned by DMA: */
+ if( fec->rx_bd[i].statCtrl & MCD_FEC_BUF_READY)
+ {
+ return( NULL );
+ }
+
+ /* increment the circular index */
+ fec->rx_bd_idx = (uint8)((i + 1) % NUM_RXBDS);
+ return(&fec->rx_bd[i]);
+}
+
+/* Return a pointer to the next empty Tx Buffer Descriptor */
+static inline MCD_bufDescFec * fec_tx_alloc(fec_if_t *fec)
+{
+ long i = fec->tx_bd_idx_next;
+ /* Check to see if the ring of BDs is full */
+ if( (fec->tx_bd[i].statCtrl & MCD_FEC_BUF_READY) )
+ return NULL;
+ /* increment the circular index */
+ fec->tx_bd_idx_next = (uint8)((fec->tx_bd_idx_next+ 1) % NUM_TXBDS);
+ return(&fec->tx_bd[i]);
+}
+
+static inline MCD_bufDescFec * fec_tx_free(fec_if_t *fec)
+{
+ long i = fec->tx_bd_idx_cur;
+
+ /* Check to see if the ring of BDs is empty */
+ if( (fec->tx_bd[i].statCtrl & MCD_FEC_BUF_READY ) )
+ return NULL;
+ /* Increment the circular index */
+ fec->tx_bd_idx_cur = (uint8)((fec->tx_bd_idx_cur + 1) % NUM_TXBDS);
+ return (&fec->tx_bd[i]);
+}
+
+
+/*
+ * Initialization. This is called when the driver is loaded. If you
+ * link the driver with main.o and init.o then this must be called
+ * driver_init() because main() calles a function with this name.
+ *
+ * You should probe for your hardware here, setup the interface
+ * structure and register your interface.
+ *
+ * This function should return 0 on success and != 0 if initialization
+ * fails.
+ */
+long
+driver_init (void)
+{
+ fec_if_t * fi;
+ static char message[100];
+ extern DMACF_COOKIE * dmac;
+
+ if( mc_dma_init() == NULL )
+ {
+ c_conws("Exit: failed to load DMA API!\n");
+ KDEBUG(("Exit: failed to load DMA API!"));
+ return( 1 );
+ }
+
+ /*
+ * Set interface name
+ */
+ strcpy (if_fec[0].name, FEC_DEVICE_NAME);
+ if_fec[0].unit = if_getfreeunit (FEC_DEVICE_NAME);
+ if_fec[0].metric = 0;
+ if_fec[0].flags = IFF_BROADCAST;
+ if_fec[0].mtu = 1500;
+ if_fec[0].timer = 0;
+ if_fec[0].hwtype = HWTYPE_ETH;
+ if_fec[0].hwlocal.len = ETH_ALEN;
+ if_fec[0].hwbrcst.len = ETH_ALEN;
+
+ /*
+ * Set interface hardware and broadcast addresses. For real ethernet
+ * drivers you must get them from the hardware of course!
+ */
+ board_get_ethaddr(if_fec[0].hwlocal.adr.bytes);
+ memcpy (if_fec[0].hwbrcst.adr.bytes, "\377\377\377\377\377\377", ETH_ALEN);
+
+ /*
+ * Set length of send and receive queue. IF_MAXQ is a good value.
+ */
+ if_fec[0].rcv.maxqlen = IF_MAXQ;
+ if_fec[0].snd.maxqlen = IF_MAXQ;
+
+ /*
+ * Setup pointers to service functions
+ */
+ if_fec[0].open = fec_open;
+ if_fec[0].close = fec_close;
+ if_fec[0].output = fec_output;
+ if_fec[0].ioctl = fec_ioctl;
+
+ /*
+ * Optional timer function that is called every 200ms.
+ */
+ if_fec[0].timeout = 0;
+
+ /*
+ * Number of packets the hardware can receive in fast succession,
+ * 0 means unlimited.
+ */
+ if_fec[0].maxpackets = NUM_RXBDS;
+
+
+ /*
+ * Here you could attach some more data your driver may need
+ */
+ if_fec[0].data = (void*)&fecif_g[0];
+ fi = &fecif_g[0];
+ memset( if_fec[0].data, sizeof(fec_if_t), 0);
+ fi->ch = 0;
+ fi->rx_dma_ch = -1;
+ fi->tx_dma_ch = -1;
+
+
+
+
+ if (NETINFO->fname)
+ {
+ if( !strcmp("FEC10.XIF", NETINFO->fname) )
+ {
+ fi->mode |= FEC_IMODE_10MBIT;
+ }
+
+ if( !strcmp("FECP.XIF", NETINFO->fname) )
+ {
+ fi->mode |= FEC_IMODE_PROMISCUOUS;
+ }
+
+ if( !strcmp("FECP10.XIF", NETINFO->fname) )
+ {
+ fi->mode |= FEC_IMODE_PROMISCUOUS | FEC_IMODE_10MBIT;
+ }
+ }
+
+ /*
+ * Register the interface.
+ */
+ if_register (&if_fec[0]);
+
+ ksprintf (message, "%s v%d.%d (%s%d - %02x:%02x:%02x:%02x:%02x:%02x) \n\r",
+ FEC_DRIVER_DESC,
+ FEC_DRIVER_MAJOR_VERSION,
+ FEC_DRIVER_MINOR_VERSION,
+ FEC_DEVICE_NAME,
+ if_fec[0].unit,
+ if_fec[0].hwlocal.adr.bytes[0],if_fec[0].hwlocal.adr.bytes[1],
+ if_fec[0].hwlocal.adr.bytes[2],if_fec[0].hwlocal.adr.bytes[3],
+ if_fec[0].hwlocal.adr.bytes[4],if_fec[0].hwlocal.adr.bytes[5]
+ );
+ c_conws (message);
+ return( 0 );
+}
+
+
+/*
+ * This gets called when someone makes an 'ifconfig up' on this interface
+ * and the interface was down before.
+ */
+static long
+fec_open (struct netif *nif)
+{
+ long res=0;
+ fec_if_t * fi = (fec_if_t*)nif->data;
+ uint8 speed = FEC_MII_100BASE_TX;
+ uint8 duplex = FEC_MII_FULL_DUPLEX;
+ uint8 mode = FEC_MODE_MII;
+
+ if( fi->mode & FEC_IMODE_10MBIT )
+ {
+ speed = FEC_MII_10BASE_T;
+ duplex = FEC_MII_HALF_DUPLEX;
+ }
+
+ if( fec_buf_init(fi) )
+ {
+ c_conws("fec_buf_init failed!");
+ fec_buf_flush(fi);
+ res = 1;
+ }
+ else
+ {
+ fec_reset(fi->ch);
+ fec_init(fi, mode, duplex, (const uint8 *)nif->hwlocal.adr.bytes);
+
+ /* Initialize the PHY interface */
+ if( (mode == FEC_MODE_MII) && (am79c874_init(fi->ch, FEC_PHY(fi->ch), speed, duplex) == 0) )
+ {
+ /* Flush the network buffers */
+ c_conws("am79c874_init failed!");
+ fec_buf_flush(fi);
+ res = 1;
+ }
+ else
+ {
+ /* Enable the multi-channel DMA tasks */
+ fec_rx_start(nif, (s8*)fi->rx_bd, fi->ch ? FEC1RX_DMA_PRI : FEC0RX_DMA_PRI);
+ fec_tx_start(nif, (s8*)fi->tx_bd, fi->ch ? FEC1TX_DMA_PRI : FEC0TX_DMA_PRI);
+ fec_enable(fi->ch);
+ }
+ }
+ return res;
+}
+
+static long fec_close( struct netif *nif )
+{
+ int level;
+ fec_if_t * fi = (fec_if_t*)nif->data;
+ /* Disable interrupts */
+ level = spl7();
+ /* Gracefully disable the receiver and transmitter */
+ fec_tx_stop(fi);
+ fec_rx_stop(fi);
+ /* Disable FEC interrupts */
+ fec_disable(fi->ch);
+ /* Flush the network buffers */
+ fec_buf_flush(fi);
+ /* Restore interrupt level */
+ spl(level);
+ return( 0 );
+}
+
+
+/*
+ * FEC output function, for general documentation look into dummyeth.c
+ */
+
+static long
+fec_output (struct netif *nif, BUF *buf, const char *hwaddr, short hwlen, short pktype)
+{
+ fec_if_t * fi = (fec_if_t*)nif->data;
+ BUF *nbuf;
+ int len,lenpad;
+ MCD_bufDescFec *dmaBuf;
+ long res = E_OK;
+
+ /* Not ready yet, failed to alloc dma channel or shutdown state? */
+ if( fi->tx_dma_ch < 0 )
+ {
+ buf_deref( buf, BUF_NORMAL );
+ return( EINTERNAL );
+ }
+
+ len = ((unsigned long)buf->dend) - ((unsigned long)buf->dstart);
+ if( len > nif->mtu || len < 1 )
+ {
+ KDEBUG(("fec_output: packet to large/small!"));
+ nif->out_errors++;
+ buf_deref( buf, BUF_NORMAL );
+ return( EINTERNAL );
+ }
+
+ /* Attach ethernet header with xif util function: */
+ nbuf = eth_build_hdr (buf, nif, hwaddr, pktype);
+ if (nbuf == 0)
+ {
+ KDEBUG(("fec_output: eth_buld_hdr failed!"));
+ nif->out_errors++;
+ res = ENOMEM;
+ goto out_err0;
+ }
+ /* packet is resized, recalculate len: */
+ len = ((unsigned long)buf->dend) - ((unsigned long)buf->dstart);
+
+ /* FEC needs at least ETH_MIN_FRM: */
+ lenpad = MAX(len, ETH_MIN_FRM );
+
+ if( lenpad > ETH_MAX_FRM )
+ {
+ KDEBUG(("fec_output: frame to large!"));
+ nif->out_errors++;
+ res = ENOMEM;
+ goto out_err1;
+ }
+
+ /* tell packet "filter" about the packet (it's more like an monitor?) */
+ if (nif->bpf)
+ bpf_input(nif, nbuf);
+
+ if( (dmaBuf = fec_tx_alloc(fi)) != NULL )
+ {
+ if( lenpad != len )
+ {
+ memset( (void*)dmaBuf->dataPointer, lenpad, 0);
+ }
+ memcpy( (void*)dmaBuf->dataPointer, nbuf->dstart, len );
+ dmaBuf->length = lenpad;
+ /* Set Frame ready for transmission */
+ dmaBuf->statCtrl |= ( MCD_FEC_BUF_READY | MCD_FEC_END_FRAME );
+ MCD_continDma(fi->tx_dma_ch);
+ }
+ else
+ {
+ KDEBUG(("bnuf_tx_alloc failed!"));
+ res = ENOMEM;
+ }
+
+out_err1:
+ buf_deref( nbuf, BUF_NORMAL );
+out_err0:
+ return res;
+}
+
+
+
+/*
+ * MintNet notifies you of some noteable IOCLT's. Usually you don't
+ * need to act on them because MintNet already has done so and only
+ * tells you that an ioctl happened.
+ *
+ * One useful thing might be SIOCGLNKFLAGS and SIOCSLNKFLAGS for setting
+ * and getting flags specific to your driver. For an example how to use
+ * them look at slip.c
+ */
+static long
+fec_ioctl (struct netif *nif, short cmd, long arg)
+{
+ struct ifreq *ifr;
+
+ switch (cmd)
+ {
+ case SIOCSIFNETMASK:
+ case SIOCSIFFLAGS:
+ case SIOCSIFADDR:
+ return 0;
+
+ case SIOCSIFMTU:
+ /*
+ * Limit MTU to 1500 bytes. MintNet has alraedy set nif->mtu
+ * to the new value, we only limit it here.
+ */
+ if (nif->mtu > ETH_MAX_DLEN)
+ nif->mtu = ETH_MAX_DLEN;
+ return 0;
+
+ case SIOCSIFOPT:
+ /*
+ * Interface configuration, handled by fec_config()
+ */
+ ifr = (struct ifreq *) arg;
+ return fec_config (nif, ifr->ifru.data);
+ }
+
+ return ENOSYS;
+}
+
+/*
+ * Interface configuration via SIOCSIFOPT. The ioctl is passed a
+ * struct ifreq *ifr. ifr->ifru.data points to a struct ifopt, which
+ * we get as the second argument here.
+ *
+ * If the user MUST configure some parameters before the interface
+ * can run make sure that fec_open() fails unless all the necessary
+ * parameters are set.
+ *
+ * Return values meaning
+ * ENOSYS option not supported
+ * ENOENT invalid option value
+ * 0 Ok
+ */
+static long
+fec_config (struct netif *nif, struct ifopt *ifo)
+{
+ fec_if_t * fi = (fec_if_t*)nif->data;
+
+# define STRNCMP(s) (strncmp ((s), ifo->option, sizeof (ifo->option)))
+
+ if (!STRNCMP ("hwaddr"))
+ {
+ uchar *cp;
+ /*
+ * Set hardware address
+ */
+ if (ifo->valtype != IFO_HWADDR)
+ return ENOENT;
+ memcpy (nif->hwlocal.adr.bytes, ifo->ifou.v_string, ETH_ALEN);
+ fec_set_address( ((fec_if_t*)nif->data)->ch, nif->hwlocal.adr.bytes );
+ cp = nif->hwlocal.adr.bytes;
+ }
+ else if (!STRNCMP ("braddr"))
+ {
+ uchar *cp;
+ /*
+ * Set broadcast address
+ */
+ if (ifo->valtype != IFO_HWADDR)
+ return ENOENT;
+ memcpy (nif->hwbrcst.adr.bytes, ifo->ifou.v_string, ETH_ALEN);
+ cp = nif->hwbrcst.adr.bytes;
+ /*KDEBUG (("fec: braddr is %x:%x:%x:%x:%x:%x",
+ cp[0], cp[1], cp[2], cp[3], cp[4], cp[5]));
+ */
+ }
+ else if (!STRNCMP ("debug"))
+ {
+ /*
+ * turn debuggin on/off
+ */
+ if (ifo->valtype != IFO_INT)
+ return ENOENT;
+ //KDEBUG (("fec: debug level is %ld", ifo->ifou.v_long));
+ if( ifo->ifou.v_long >= 2 )
+ {
+ fec_reg_dump( fi->ch );
+ }
+ }
+ else if(!STRNCMP("promisc"))
+ {
+ // TBD restart FEC and set promisc mode
+ if (ifo->valtype != IFO_STRING)
+ return ENOENT;
+ }
+ else if (!STRNCMP ("log"))
+ {
+ /*
+ * set log file
+ */
+ if (ifo->valtype != IFO_STRING)
+ return ENOENT;
+ //KDEBUG (("fec: log file is %s", ifo->ifou.v_string));
+ }
+
+ return ENOSYS;
+}
+
+
diff -aurN -x CVS ./xif.orig//fec/fec.h ./xif/fec/fec.h
--- ./xif.orig//fec/fec.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/fec.h 2011-11-10 21:24:32.000000000 +0100
@@ -0,0 +1,119 @@
+/*
+ * File: fec.h
+ * Purpose: Driver for the Fast Ethernet Controller (FEC)
+ *
+ * Notes:
+ */
+
+#ifndef _FEC_H_
+#define _FEC_H_
+
+
+#include "platform/types.h"
+#include "platform/board.h"
+
+/* Driver meta defines: */
+
+#define FEC_DRIVER_MAJOR_VERSION 0
+#define FEC_DRIVER_MINOR_VERSION 1
+
+#define FEC_DRIVER_DESC "FEC Ethernet driver"
+#ifndef FEC_DRIVER
+ #define FEC_DRIVER "fec.xif"
+#endif
+
+#define FEC_DEVICE_NAME "eth"
+
+
+#ifndef FEC_CHANNEL
+ #define FEC_CHANNEL 0
+#endif
+
+
+#define FEC_DEBUG 1
+#define FEC_VERBOSE 1
+#ifdef FEC_VERBOSE
+#define FEC_DEBUG 1
+#endif
+
+
+/*
+#ifdef FEC_DEBUG
+#define FEC_PROMISCUOUS
+#endif
+*/
+
+#ifdef FEC_DEBUG
+#define KDEBUG(x) KERNEL_DEBUG x
+#else
+ #define KDEBUG(x)
+#endif
+
+
+/* MII Speed Settings */
+#define FEC_MII_10BASE_T 0
+#define FEC_MII_100BASE_TX 1
+
+/* MII Duplex Settings */
+#define FEC_MII_HALF_DUPLEX 0
+#define FEC_MII_FULL_DUPLEX 1
+
+/* Timeout for MII communications */
+#define FEC_MII_TIMEOUT 0x10000
+
+/* External Interface Modes */
+#define FEC_MODE_7WIRE 0
+#define FEC_MODE_MII 1
+#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */
+#define FEC_MODE_RMII 3
+#define FEC_MODE_RMII_LOOPBACK 4 /* Internal Loopback */
+
+/* Intern driver modes: */
+#define FEC_IMODE_PROMISCUOUS 1
+#define FEC_IMODE_10MBIT 2
+
+/* ------------------------ Prototypes ------------------------------------ */
+long fec_mii_write(uint8 a, uint8 b, uint8 c, uint16 d);
+long fec_mii_read(uint8, uint8, uint8, uint16 *);
+void fec_mii_init(uint8, uint32);
+void fec_duplex (uint8, uint8);
+
+
+/*
+ * Ethernet Info
+ */
+#define FEC_PHY0 (0x00)
+#define FEC_PHY1 (0x01)
+#define FEC_PHY(x) ((x == 0) ? FEC_PHY0 : FEC_PHY1)
+
+#define phy_init am79c874_init
+
+/* Interrupt Priorities */
+#define DMA_INTC_LVL 5
+#define DMA_INTC_PRI 3
+#define FEC_INTC_LVL 5
+#define FEC0_INTC_PRI 1
+#define FEC1_INTC_PRI 0
+
+/* DMA Task Priorities */
+#define FEC0TX_DMA_PRI 6
+#define FEC0RX_DMA_PRI 5
+#define FEC1TX_DMA_PRI 4
+#define FEC1RX_DMA_PRI 3
+
+/* Number of DMA FEC Buffers to allocate */
+#define NUM_RXBDS (20)
+#define NUM_TXBDS (20)
+
+/* size of data bound to each desriptor: */
+#define RX_BUFFER_SIZE (2048)
+#define TX_BUFFER_SIZE (1520)
+
+/* Error flags within RX Buffer descriptors statCtrl: */
+#define RX_BD_NO 0x0010
+#define RX_BD_CR 0x0004
+#define RX_BD_OV 0x0002
+#define RX_BD_TR 0x0001
+#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)
+
+#endif /* _FEC_H_ */
diff -aurN -x CVS ./xif.orig//fec/Makefile ./xif/fec/Makefile
--- ./xif.orig//fec/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/Makefile 2011-09-11 21:37:55.000000000 +0200
@@ -0,0 +1,43 @@
+#
+# Makefile for
+#
+TARGET = fec.xif
+
+GENFILES = $(TARGET)
+
+SHELL = /bin/sh
+SUBDIRS =
+
+srcdir = .
+top_srcdir = ../../..
+subdir = fec
+
+default: all
+
+include $(top_srcdir)/CONFIGVARS
+include $(top_srcdir)/RULES
+include $(top_srcdir)/PHONY
+
+all-here: $(TARGET)
+
+# default overwrites
+INCLUDES = -I../.. -I$(top_srcdir)
+XIF_DEFINITIONS =
+DEFINITIONS = -D__KERNEL_XDD__ $(XIF_DEFINITIONS)
+
+LD = $(CC) -mshort -nostdlib -Wl,--entry -Wl,_init
+LIBS = $(LIBKERN) -lgcc
+CPU="020-60"
+
+# default definitions
+OBJS = $(addsuffix .o, $(basename $(notdir $(FECDMA_SRCS) $(COMMON_SRCS))))
+
+main.o: ../main.c
+ $(CC) -o $@ $(CFLAGS) -c ../main.c
+
+# generic driver target
+$(TARGET): $(OBJS) $(LIBKERNSTMP)
+ $(LD) $(CFLAGS) -o $@ $(OBJS) $(LIBS)
+
+
+include $(top_srcdir)/DEPENDENCIES
diff -aurN -x CVS ./xif.orig//fec/MISCFILES ./xif/fec/MISCFILES
--- ./xif.orig//fec/MISCFILES 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/MISCFILES 2011-11-08 00:15:47.000000000 +0100
@@ -0,0 +1,4 @@
+# This file gets included by the Makefile in this directory to determine
+# the files that should go both into source and binary distributions.
+
+MISCFILES = README
diff -aurN -x CVS ./xif.orig//fec/platform/board.h ./xif/fec/platform/board.h
--- ./xif.orig//fec/platform/board.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/board.h 2011-11-08 00:20:04.000000000 +0100
@@ -0,0 +1,45 @@
+#ifndef CF_BOARD_H
+#define CF_BOARD_H
+
+#define __MBAR ((volatile unsigned char*)0xff000000)
+
+/*
+ FireTOS Flash paramters, like MAC Address
+ (configure via FireBee CPX)
+*/
+#define PARAMS_ADDRESS 0xE0002000
+
+/*
+ * System Bus Clock Info
+ */
+#define SYSTEM_CLOCK 133
+
+/*
+ CPU Type
+*/
+#define MCF547X
+
+#include "types.h"
+#include "mcf548x_fec.h"
+#include "mcf548x_dma.h"
+#include "mcf548x_gpio.h"
+#include "mcf548x_intc.h"
+#include "dma.h"
+
+/*
+ * Structure definition for the Parameters
+ */
+#define FILENAME_SIZE (40)
+typedef struct
+{
+ unsigned long baud;
+ unsigned char client[4];
+ unsigned char server[4];
+ unsigned char gateway[4];
+ unsigned char netmask[4];
+ unsigned char netcfg[4];
+ unsigned char ethaddr[6];
+ char filename[FILENAME_SIZE];
+} PARAM;
+
+#endif
diff -aurN -x CVS ./xif.orig//fec/platform/dma.h ./xif/fec/platform/dma.h
--- ./xif.orig//fec/platform/dma.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/dma.h 2011-11-03 18:34:20.000000000 +0100
@@ -0,0 +1,362 @@
+
+
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+/*
+ * Portability typedefs
+ */
+typedef signed long s32;
+typedef unsigned long u32;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed char s8;
+typedef unsigned char u8;
+
+
+
+/* Chained buffer descriptor */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+ u32 flags; /* flags describing the DMA */
+ u32 csumResult; /* checksum from checksumming performed since last checksum reset */
+ s8 *srcAddr; /* the address to move data from */
+ s8 *destAddr; /* the address to move data to */
+ s8 *lastDestAddr; /* the last address written to */
+ u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
+ MCD_bufDesc *next; /* next buffer descriptor in chain */
+ u32 info; /* private information about this descriptor; DMA does not affect it */
+};
+
+/* Progress Query struct */
+typedef volatile struct MCD_XferProg_struct {
+ s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
+ s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
+ u32 dmaSize; /* the amount of data transferred for the current buffer */
+ MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
+} MCD_XferProg;
+
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+ u16 statCtrl;
+ u16 length;
+ u32 dataPointer;
+} MCD_bufDescFec;
+
+
+typedef struct dma_cookie
+{
+ s32 version; /* 0x0101 for example */
+ s32 magic; /* 'DMAC' */
+ s32 (*dma_set_initiator)(s32 initiator);
+ u32 (*dma_get_initiator)(s32 requestor);
+ void (*dma_free_initiator)(s32 requestor);
+ s32 (*dma_set_channel)(s32 requestor, void (*handler)(void));
+ s32 (*dma_get_channel)(s32 requestor);
+ void (*dma_free_channel)(s32 requestor);
+ void (*dma_clear_channel)(s32 channel);
+ s32 (*MCD_startDma)(long channel, s8 *srcAddr, u32 srcIncr, s8 *destAddr, u32 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, long priority, u32 flags, u32 funcDesc);
+ s32 (*MCD_dmaStatus)(s32 channel);
+ s32 (*MCD_XferProgrQuery)(s32 channel, MCD_XferProg *progRep);
+ s32 (*MCD_killDma)(s32 channel);
+ s32 (*MCD_continDma)(s32 channel);
+ s32 (*MCD_pauseDma)(s32 channel);
+ s32 (*MCD_resumeDma)(s32 channel);
+ s32 (*MCD_csumQuery)(s32 channel, u32 *csum);
+ void *(*dma_alloc)(ulong size);
+ long (*dma_free)(void * mem);
+} DMACF_COOKIE;
+
+/********************************************************************/
+
+
+/********************************************************************/
+
+/*
+ * Create identifiers for each initiator/requestor
+ */
+#define DMA_ALWAYS (0)
+#define DMA_DSPI_RX (1)
+#define DMA_DSPI_TX (2)
+#define DMA_DREQ0 (3)
+#define DMA_PSC0_RX (4)
+#define DMA_PSC0_TX (5)
+#define DMA_USBEP0 (6)
+#define DMA_USBEP1 (7)
+#define DMA_USBEP2 (8)
+#define DMA_USBEP3 (9)
+#define DMA_PCI_TX (10)
+#define DMA_PCI_RX (11)
+#define DMA_PSC1_RX (12)
+#define DMA_PSC1_TX (13)
+#define DMA_I2C_RX (14)
+#define DMA_I2C_TX (15)
+#define DMA_FEC0_RX (16)
+#define DMA_FEC0_TX (17)
+#define DMA_FEC1_RX (18)
+#define DMA_FEC1_TX (19)
+#define DMA_DREQ1 (20)
+#define DMA_CTM0 (21)
+#define DMA_CTM1 (22)
+#define DMA_CTM2 (23)
+#define DMA_CTM3 (24)
+#define DMA_CTM4 (25)
+#define DMA_CTM5 (26)
+#define DMA_CTM6 (27)
+#define DMA_CTM7 (28)
+#define DMA_USBEP4 (29)
+#define DMA_USBEP5 (30)
+#define DMA_USBEP6 (31)
+#define DMA_PSC2_RX (32)
+#define DMA_PSC2_TX (33)
+#define DMA_PSC3_RX (34)
+#define DMA_PSC3_TX (35)
+#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
+#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
+
+/********************************************************************/
+
+
+
+/*
+ * Number of DMA channels
+ */
+#define NCHANNELS 16
+
+/*
+ * PTD contrl reg bits
+ */
+#define PTD_CTL_TSK_PRI 0x8000
+#define PTD_CTL_COMM_PREFETCH 0x0001
+
+/*
+ * Task Control reg bits and field masks
+ */
+#define TASK_CTL_EN 0x8000
+#define TASK_CTL_VALID 0x4000
+#define TASK_CTL_ALWAYS 0x2000
+#define TASK_CTL_INIT_MASK 0x1f00
+#define TASK_CTL_ASTRT 0x0080
+#define TASK_CTL_HIPRITSKEN 0x0040
+#define TASK_CTL_HLDINITNUM 0x0020
+#define TASK_CTL_ASTSKNUM_MASK 0x000f
+
+/*
+ * Priority reg bits and field masks
+ */
+#define PRIORITY_HLD 0x80
+#define PRIORITY_PRI_MASK 0x07
+
+/*
+ * Debug Control reg bits and field masks
+ */
+#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
+#define DBG_CTL_AUTO_ARM 0x00008000
+#define DBG_CTL_BREAK 0x00004000
+#define DBG_CTL_COMP1_TYP_MASK 0x00003800
+#define DBG_CTL_COMP2_TYP_MASK 0x00000070
+#define DBG_CTL_EXT_BREAK 0x00000004
+#define DBG_CTL_INT_BREAK 0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
+ have initiators asserted */
+
+
+/*
+ * General return values
+ */
+#define MCD_OK 0
+#define MCD_ERROR -1
+#define MCD_TABLE_UNALIGNED -2
+#define MCD_CHANNEL_INVALID -3
+
+/*
+ * MCD_initDma input flags
+ */
+#define MCD_RELOC_TASKS 0x00000001
+#define MCD_NO_RELOC_TASKS 0x00000000
+#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel
+ */
+#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
+#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
+#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
+#define MCD_PAUSED 4 /* DMA active but it is currently paused */
+#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
+#define MCD_DONE 6 /* the most recent DMA has completed. */
+
+
+/*
+ * Constants for the funcDesc parameter
+ */
+/* Byte swapping: */
+#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
+#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
+#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
+ each 32-bit data value being DMAed.*/
+#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
+ 16-bit half of each 32-bit data value DMAed */
+#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
+#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
+
+/* CRCing: */
+#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
+#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
+#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
+#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
+#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
+
+#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/*
+ * Constants for the flags parameter
+ */
+#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
+#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
+#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
+#define MCD_TT_FLAGS_MASK 0x000000ff
+#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
+#define MCD_CHAIN_DMA /* TBD */
+#define MCD_EU_DMA /* TBD */
+#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
+#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
+
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
+#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
+#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
+#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
+ last byte of data in buffer */
+#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
+ prior to performing the DMA. */
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY 0x8000
+#define MCD_FEC_WRAP 0x2000
+#define MCD_FEC_INTERRUPT 0x1000
+#define MCD_FEC_END_FRAME 0x0800
+
+
+/*
+ * Defines for general intuitiveness
+ */
+
+#define MCD_TRUE 1
+#define MCD_FALSE 0
+
+/*
+ * Three different cases for destination and source.
+ */
+#define MINUS1 -1
+#define ZERO 0
+#define PLUS1 1
+
+
+/*************************************************************************/
+/*
+ * API function Prototypes - see MCD_dmaApi.c for further notes
+ */
+
+/*
+ * MCD_startDma starts a particular kind of DMA .
+ */
+
+#define MCD_startDma(\
+ channel, srcAddr, srcIncr,\
+ destAddr, destIncr, dmaSize,\
+ xferSize, initiator, priority,\
+ flags, funcDesc ) \
+((dmac->MCD_startDma) ( \
+ channel, srcAddr, srcIncr, \
+ destAddr, destIncr, dmaSize, \
+ xferSize, initiator, priority, \
+ flags, funcDesc))
+
+
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
+ * setting up some global settings
+ */
+#define MCD_initDma(sDmaBarAddr, taskTableDest, flags) \
+ (dmac->MCD_initDma)(sDmaBarAddr, taskTableDest, flags))
+
+/*
+ * MCD_dmaStatus() returns the status of the DMA on the requested channel.
+ */
+#define MCD_dmaStatus(ch) ((dmac->MCD_dmaStatus)(ch))
+
+/*
+ * MCD_XferProgrQuery() returns progress of DMA on requested channel
+ */
+#define MCD_XferProgrQuery (channel, progRep) \
+ ((dmac->MCD_XferProgrQuery(channel, progRep))
+
+/*
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+#define MCD_killDma(channel) ((dmac->MCD_killDma)(channel))
+
+/*
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+#define MCD_continDma(channel) ((dmac->MCD_continDma)(channel))
+
+/*
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel).
+ */
+#define MCD_pauseDma (channel) ((dmac->MCD_pauseDma)( channel ))
+
+/*
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+#define MCD_resumeDma(channel) ((dmac->MCD_resumeDma)(channel))
+
+
+/*
+ * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
+ */
+#define MCD_csumQuery(channel, csum) ((dmac->MCD_csumQuery)( channel, csum))
+
+/*
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+#define MCD_getCodeSize(void) ((dmac->MCD_getCodeSize)())
+
+
+/* DMA Utils: */
+#define dma_set_initiator(ini) ((dmac->dma_set_initiator)(ini))
+#define dma_get_initiator(ini) ((dmac->dma_get_initiator)(ini))
+#define dma_free_initiator(ini) ((dmac->dma_free_initiator)(ini))
+#define dma_set_channel( requestor, handler ) ((dmac->dma_set_channel)(requestor, handler))
+#define dma_get_channel(requestor) ((dmac->dma_get_channel)(requestor))
+#define dma_free_channel(requestor) ((dmac->dma_free_channel)(requestor))
+#define dma_clear_channel(channel) ((dmac->dma_clear_channel)(channel))
+
+#define dma_alloc(size) ((dmac->dma_alloc)(size))
+#define dma_free(mem) ((dmac->dma_free)(mem))
+
+DMACF_COOKIE * mc_dma_init( void );
+
+extern DMACF_COOKIE * dmac;
+
+#endif /* _MCD_API_H */
+
diff -aurN -x CVS ./xif.orig//fec/platform/mcf548x_dma.h ./xif/fec/platform/mcf548x_dma.h
--- ./xif.orig//fec/platform/mcf548x_dma.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/mcf548x_dma.h 2004-08-10 11:26:08.000000000 +0200
@@ -0,0 +1,131 @@
+/*
+ * File: mcf548x_dma.h
+ * Purpose: Register and bit definitions for the MCF548X
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __MCF548X_DMA_H__
+#define __MCF548X_DMA_H__
+
+/*********************************************************************
+*
+* Multi-Channel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR (*(vuint32*)(void*)(&__MBAR[0x008000]))
+#define MCF_DMA_CP (*(vuint32*)(void*)(&__MBAR[0x008004]))
+#define MCF_DMA_EP (*(vuint32*)(void*)(&__MBAR[0x008008]))
+#define MCF_DMA_VP (*(vuint32*)(void*)(&__MBAR[0x00800C]))
+#define MCF_DMA_DIPR (*(vuint32*)(void*)(&__MBAR[0x008014]))
+#define MCF_DMA_DIMR (*(vuint32*)(void*)(&__MBAR[0x008018]))
+#define MCF_DMA_TCR0 (*(vuint16*)(void*)(&__MBAR[0x00801C]))
+#define MCF_DMA_TCR1 (*(vuint16*)(void*)(&__MBAR[0x00801E]))
+#define MCF_DMA_TCR2 (*(vuint16*)(void*)(&__MBAR[0x008020]))
+#define MCF_DMA_TCR3 (*(vuint16*)(void*)(&__MBAR[0x008022]))
+#define MCF_DMA_TCR4 (*(vuint16*)(void*)(&__MBAR[0x008024]))
+#define MCF_DMA_TCR5 (*(vuint16*)(void*)(&__MBAR[0x008026]))
+#define MCF_DMA_TCR6 (*(vuint16*)(void*)(&__MBAR[0x008028]))
+#define MCF_DMA_TCR7 (*(vuint16*)(void*)(&__MBAR[0x00802A]))
+#define MCF_DMA_TCR8 (*(vuint16*)(void*)(&__MBAR[0x00802C]))
+#define MCF_DMA_TCR9 (*(vuint16*)(void*)(&__MBAR[0x00802E]))
+#define MCF_DMA_TCR10 (*(vuint16*)(void*)(&__MBAR[0x008030]))
+#define MCF_DMA_TCR11 (*(vuint16*)(void*)(&__MBAR[0x008032]))
+#define MCF_DMA_TCR12 (*(vuint16*)(void*)(&__MBAR[0x008034]))
+#define MCF_DMA_TCR13 (*(vuint16*)(void*)(&__MBAR[0x008036]))
+#define MCF_DMA_TCR14 (*(vuint16*)(void*)(&__MBAR[0x008038]))
+#define MCF_DMA_TCR15 (*(vuint16*)(void*)(&__MBAR[0x00803A]))
+#define MCF_DMA_TCRn(x) (*(vuint16*)(void*)(&__MBAR[0x00801C+((x)*0x002)]))
+#define MCF_DMA_IMCR (*(vuint32*)(void*)(&__MBAR[0x00805C]))
+#define MCF_DMA_PTDDBG (*(vuint32*)(void*)(&__MBAR[0x008080]))
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK0 (0x00000001)
+#define MCF_DMA_DIPR_TASK1 (0x00000002)
+#define MCF_DMA_DIPR_TASK2 (0x00000004)
+#define MCF_DMA_DIPR_TASK3 (0x00000008)
+#define MCF_DMA_DIPR_TASK4 (0x00000010)
+#define MCF_DMA_DIPR_TASK5 (0x00000020)
+#define MCF_DMA_DIPR_TASK6 (0x00000040)
+#define MCF_DMA_DIPR_TASK7 (0x00000080)
+#define MCF_DMA_DIPR_TASK8 (0x00000100)
+#define MCF_DMA_DIPR_TASK9 (0x00000200)
+#define MCF_DMA_DIPR_TASK10 (0x00000400)
+#define MCF_DMA_DIPR_TASK11 (0x00000800)
+#define MCF_DMA_DIPR_TASK12 (0x00001000)
+#define MCF_DMA_DIPR_TASK13 (0x00002000)
+#define MCF_DMA_DIPR_TASK14 (0x00004000)
+#define MCF_DMA_DIPR_TASK15 (0x00008000)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK0 (0x00000001)
+#define MCF_DMA_DIMR_TASK1 (0x00000002)
+#define MCF_DMA_DIMR_TASK2 (0x00000004)
+#define MCF_DMA_DIMR_TASK3 (0x00000008)
+#define MCF_DMA_DIMR_TASK4 (0x00000010)
+#define MCF_DMA_DIMR_TASK5 (0x00000020)
+#define MCF_DMA_DIMR_TASK6 (0x00000040)
+#define MCF_DMA_DIMR_TASK7 (0x00000080)
+#define MCF_DMA_DIMR_TASK8 (0x00000100)
+#define MCF_DMA_DIMR_TASK9 (0x00000200)
+#define MCF_DMA_DIMR_TASK10 (0x00000400)
+#define MCF_DMA_DIMR_TASK11 (0x00000800)
+#define MCF_DMA_DIMR_TASK12 (0x00001000)
+#define MCF_DMA_DIMR_TASK13 (0x00002000)
+#define MCF_DMA_DIMR_TASK14 (0x00004000)
+#define MCF_DMA_DIMR_TASK15 (0x00008000)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0)
+#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2)
+#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4)
+#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6)
+#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8)
+#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10)
+#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12)
+#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14)
+#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16)
+#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18)
+#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20)
+#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22)
+#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24)
+#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26)
+#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28)
+#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30)
+#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000)
+#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000)
+#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020)
+#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080)
+#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100)
+#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000)
+#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400)
+#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000)
+#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000)
+#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000)
+#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000)
+#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000)
+#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000)
+#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000)
+#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000)
+#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000)
+#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000)
+#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000)
+#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000)
+#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000)
+#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000)
+#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000)
+#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000)
+#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000)
+#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000)
+#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000)
+#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000)
+#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000)
+#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000)
+#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000)
+
+/********************************************************************/
+
+#endif /* __MCF548X_DMA_H__ */
diff -aurN -x CVS ./xif.orig//fec/platform/mcf548x_fec.h ./xif/fec/platform/mcf548x_fec.h
--- ./xif.orig//fec/platform/mcf548x_fec.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/mcf548x_fec.h 2011-10-11 21:14:02.000000000 +0200
@@ -0,0 +1,495 @@
+/*
+ * File: mcf548x_fec.h
+ * Purpose: Register and bit definitions for the MCF548X
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __MCF548X_FEC_H__
+#define __MCF548X_FEC_H__
+
+/*********************************************************************
+*
+* Fast Ethernet Controller (FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC_EIR0 (*(vuint32*)(void*)(&__MBAR[0x009004]))
+#define MCF_FEC_EIMR0 (*(vuint32*)(void*)(&__MBAR[0x009008]))
+#define MCF_FEC_ECR0 (*(vuint32*)(void*)(&__MBAR[0x009024]))
+#define MCF_FEC_MMFR0 (*(vuint32*)(void*)(&__MBAR[0x009040]))
+#define MCF_FEC_MSCR0 (*(vuint32*)(void*)(&__MBAR[0x009044]))
+#define MCF_FEC_MIBC0 (*(vuint32*)(void*)(&__MBAR[0x009064]))
+#define MCF_FEC_RCR0 (*(vuint32*)(void*)(&__MBAR[0x009084]))
+#define MCF_FEC_R_HASH0 (*(vuint32*)(void*)(&__MBAR[0x009088]))
+#define MCF_FEC_TCR0 (*(vuint32*)(void*)(&__MBAR[0x0090C4]))
+#define MCF_FEC_PALR0 (*(vuint32*)(void*)(&__MBAR[0x0090E4]))
+#define MCF_FEC_PAUR0 (*(vuint32*)(void*)(&__MBAR[0x0090E8]))
+#define MCF_FEC_OPD0 (*(vuint32*)(void*)(&__MBAR[0x0090EC]))
+#define MCF_FEC_IAUR0 (*(vuint32*)(void*)(&__MBAR[0x009118]))
+#define MCF_FEC_IALR0 (*(vuint32*)(void*)(&__MBAR[0x00911C]))
+#define MCF_FEC_GAUR0 (*(vuint32*)(void*)(&__MBAR[0x009120]))
+#define MCF_FEC_GALR0 (*(vuint32*)(void*)(&__MBAR[0x009124]))
+#define MCF_FEC_FECTFWR0 (*(vuint32*)(void*)(&__MBAR[0x009144]))
+#define MCF_FEC_FECRFDR0 (*(vuint32*)(void*)(&__MBAR[0x009184]))
+#define MCF_FEC_FECRFSR0 (*(vuint32*)(void*)(&__MBAR[0x009188]))
+#define MCF_FEC_FECRFCR0 (*(vuint32*)(void*)(&__MBAR[0x00918C]))
+#define MCF_FEC_FECRLRFP0 (*(vuint32*)(void*)(&__MBAR[0x009190]))
+#define MCF_FEC_FECRLWFP0 (*(vuint32*)(void*)(&__MBAR[0x009194]))
+#define MCF_FEC_FECRFAR0 (*(vuint32*)(void*)(&__MBAR[0x009198]))
+#define MCF_FEC_FECRFRP0 (*(vuint32*)(void*)(&__MBAR[0x00919C]))
+#define MCF_FEC_FECRFWP0 (*(vuint32*)(void*)(&__MBAR[0x0091A0]))
+#define MCF_FEC_FECTFDR0 (*(vuint32*)(void*)(&__MBAR[0x0091A4]))
+#define MCF_FEC_FECTFSR0 (*(vuint32*)(void*)(&__MBAR[0x0091A8]))
+#define MCF_FEC_FECTFCR0 (*(vuint32*)(void*)(&__MBAR[0x0091AC]))
+#define MCF_FEC_FECTLRFP0 (*(vuint32*)(void*)(&__MBAR[0x0091B0]))
+#define MCF_FEC_FECTLWFP0 (*(vuint32*)(void*)(&__MBAR[0x0091B4]))
+#define MCF_FEC_FECTFAR0 (*(vuint32*)(void*)(&__MBAR[0x0091B8]))
+#define MCF_FEC_FECTFRP0 (*(vuint32*)(void*)(&__MBAR[0x0091BC]))
+#define MCF_FEC_FECTFWP0 (*(vuint32*)(void*)(&__MBAR[0x0091C0]))
+#define MCF_FEC_FRST0 (*(vuint32*)(void*)(&__MBAR[0x0091C4]))
+#define MCF_FEC_CTCWR0 (*(vuint32*)(void*)(&__MBAR[0x0091C8]))
+#define MCF_FEC_RMON_T_DROP0 (*(vuint32*)(void*)(&__MBAR[0x009200]))
+#define MCF_FEC_RMON_T_PACKETS0 (*(vuint32*)(void*)(&__MBAR[0x009204]))
+#define MCF_FEC_RMON_T_BC_PKT0 (*(vuint32*)(void*)(&__MBAR[0x009208]))
+#define MCF_FEC_RMON_T_MC_PKT0 (*(vuint32*)(void*)(&__MBAR[0x00920C]))
+#define MCF_FEC_RMON_T_CRC_ALIGN0 (*(vuint32*)(void*)(&__MBAR[0x009210]))
+#define MCF_FEC_RMON_T_UNDERSIZE0 (*(vuint32*)(void*)(&__MBAR[0x009214]))
+#define MCF_FEC_RMON_T_OVERSIZE0 (*(vuint32*)(void*)(&__MBAR[0x009218]))
+#define MCF_FEC_RMON_T_FRAG0 (*(vuint32*)(void*)(&__MBAR[0x00921C]))
+#define MCF_FEC_RMON_T_JAB0 (*(vuint32*)(void*)(&__MBAR[0x009220]))
+#define MCF_FEC_RMON_T_COL0 (*(vuint32*)(void*)(&__MBAR[0x009224]))
+#define MCF_FEC_RMON_T_P640 (*(vuint32*)(void*)(&__MBAR[0x009228]))
+#define MCF_FEC_RMON_T_P65TO1270 (*(vuint32*)(void*)(&__MBAR[0x00922C]))
+#define MCF_FEC_RMON_T_P128TO2550 (*(vuint32*)(void*)(&__MBAR[0x009230]))
+#define MCF_FEC_RMON_T_P256TO5110 (*(vuint32*)(void*)(&__MBAR[0x009234]))
+#define MCF_FEC_RMON_T_P512TO10230 (*(vuint32*)(void*)(&__MBAR[0x009238]))
+#define MCF_FEC_RMON_T_P1024TO20470 (*(vuint32*)(void*)(&__MBAR[0x00923C]))
+#define MCF_FEC_RMON_T_P_GTE20480 (*(vuint32*)(void*)(&__MBAR[0x009240]))
+#define MCF_FEC_RMON_T_OCTETS0 (*(vuint32*)(void*)(&__MBAR[0x009244]))
+#define MCF_FEC_IEEE_T_DROP0 (*(vuint32*)(void*)(&__MBAR[0x009248]))
+#define MCF_FEC_IEEE_T_FRAME_OK0 (*(vuint32*)(void*)(&__MBAR[0x00924C]))
+#define MCF_FEC_IEEE_T_1COL0 (*(vuint32*)(void*)(&__MBAR[0x009250]))
+#define MCF_FEC_IEEE_T_MCOL0 (*(vuint32*)(void*)(&__MBAR[0x009254]))
+#define MCF_FEC_IEEE_T_DEF0 (*(vuint32*)(void*)(&__MBAR[0x009258]))
+#define MCF_FEC_IEEE_T_LCOL0 (*(vuint32*)(void*)(&__MBAR[0x00925C]))
+#define MCF_FEC_IEEE_T_EXCOL0 (*(vuint32*)(void*)(&__MBAR[0x009260]))
+#define MCF_FEC_IEEE_T_MACERR0 (*(vuint32*)(void*)(&__MBAR[0x009264]))
+#define MCF_FEC_IEEE_T_CSERR0 (*(vuint32*)(void*)(&__MBAR[0x009268]))
+#define MCF_FEC_IEEE_T_SQE0 (*(vuint32*)(void*)(&__MBAR[0x00926C]))
+#define MCF_FEC_IEEE_T_FDXFC0 (*(vuint32*)(void*)(&__MBAR[0x009270]))
+#define MCF_FEC_IEEE_T_OCTETS_OK0 (*(vuint32*)(void*)(&__MBAR[0x009274]))
+#define MCF_FEC_RMON_R_PACKETS0 (*(vuint32*)(void*)(&__MBAR[0x009284]))
+#define MCF_FEC_RMON_R_BC_PKT0 (*(vuint32*)(void*)(&__MBAR[0x009288]))
+#define MCF_FEC_RMON_R_MC_PKT0 (*(vuint32*)(void*)(&__MBAR[0x00928C]))
+#define MCF_FEC_RMON_R_CRC_ALIGN0 (*(vuint32*)(void*)(&__MBAR[0x009290]))
+#define MCF_FEC_RMON_R_UNDERSIZE0 (*(vuint32*)(void*)(&__MBAR[0x009294]))
+#define MCF_FEC_RMON_R_OVERSIZE0 (*(vuint32*)(void*)(&__MBAR[0x009298]))
+#define MCF_FEC_RMON_R_FRAG0 (*(vuint32*)(void*)(&__MBAR[0x00929C]))
+#define MCF_FEC_RMON_R_JAB0 (*(vuint32*)(void*)(&__MBAR[0x0092A0]))
+#define MCF_FEC_RMON_R_RESVD_00 (*(vuint32*)(void*)(&__MBAR[0x0092A4]))
+#define MCF_FEC_RMON_R_P640 (*(vuint32*)(void*)(&__MBAR[0x0092A8]))
+#define MCF_FEC_RMON_R_P65TO1270 (*(vuint32*)(void*)(&__MBAR[0x0092AC]))
+#define MCF_FEC_RMON_R_P128TO2550 (*(vuint32*)(void*)(&__MBAR[0x0092B0]))
+#define MCF_FEC_RMON_R_P256TO5110 (*(vuint32*)(void*)(&__MBAR[0x0092B4]))
+#define MCF_FEC_RMON_R_512TO10230 (*(vuint32*)(void*)(&__MBAR[0x0092B8]))
+#define MCF_FEC_RMON_R_1024TO20470 (*(vuint32*)(void*)(&__MBAR[0x0092BC]))
+#define MCF_FEC_RMON_R_P_GTE20480 (*(vuint32*)(void*)(&__MBAR[0x0092C0]))
+#define MCF_FEC_RMON_R_OCTETS0 (*(vuint32*)(void*)(&__MBAR[0x0092C4]))
+#define MCF_FEC_IEEE_R_DROP0 (*(vuint32*)(void*)(&__MBAR[0x0092C8]))
+#define MCF_FEC_IEEE_R_FRAME_OK0 (*(vuint32*)(void*)(&__MBAR[0x0092CC]))
+#define MCF_FEC_IEEE_R_CRC0 (*(vuint32*)(void*)(&__MBAR[0x0092D0]))
+#define MCF_FEC_IEEE_R_ALIGN0 (*(vuint32*)(void*)(&__MBAR[0x0092D4]))
+#define MCF_FEC_IEEE_R_MACERR0 (*(vuint32*)(void*)(&__MBAR[0x0092D8]))
+#define MCF_FEC_IEEE_R_FDXFC0 (*(vuint32*)(void*)(&__MBAR[0x0092DC]))
+#define MCF_FEC_IEEE_R_OCTETS_OK0 (*(vuint32*)(void*)(&__MBAR[0x0092E0]))
+#define MCF_FEC_EIR1 (*(vuint32*)(void*)(&__MBAR[0x009804]))
+#define MCF_FEC_EIMR1 (*(vuint32*)(void*)(&__MBAR[0x009808]))
+#define MCF_FEC_ECR1 (*(vuint32*)(void*)(&__MBAR[0x009824]))
+#define MCF_FEC_MMFR1 (*(vuint32*)(void*)(&__MBAR[0x009840]))
+#define MCF_FEC_MSCR1 (*(vuint32*)(void*)(&__MBAR[0x009844]))
+#define MCF_FEC_MIBC1 (*(vuint32*)(void*)(&__MBAR[0x009864]))
+#define MCF_FEC_RCR1 (*(vuint32*)(void*)(&__MBAR[0x009884]))
+#define MCF_FEC_R_HASH1 (*(vuint32*)(void*)(&__MBAR[0x009888]))
+#define MCF_FEC_TCR1 (*(vuint32*)(void*)(&__MBAR[0x0098C4]))
+#define MCF_FEC_PALR1 (*(vuint32*)(void*)(&__MBAR[0x0098E4]))
+#define MCF_FEC_PAUR1 (*(vuint32*)(void*)(&__MBAR[0x0098E8]))
+#define MCF_FEC_OPD1 (*(vuint32*)(void*)(&__MBAR[0x0098EC]))
+#define MCF_FEC_IAUR1 (*(vuint32*)(void*)(&__MBAR[0x009918]))
+#define MCF_FEC_IALR1 (*(vuint32*)(void*)(&__MBAR[0x00991C]))
+#define MCF_FEC_GAUR1 (*(vuint32*)(void*)(&__MBAR[0x009920]))
+#define MCF_FEC_GALR1 (*(vuint32*)(void*)(&__MBAR[0x009924]))
+#define MCF_FEC_FECTFWR1 (*(vuint32*)(void*)(&__MBAR[0x009944]))
+#define MCF_FEC_FECRFDR1 (*(vuint32*)(void*)(&__MBAR[0x009984]))
+#define MCF_FEC_FECRFSR1 (*(vuint32*)(void*)(&__MBAR[0x009988]))
+#define MCF_FEC_FECRFCR1 (*(vuint32*)(void*)(&__MBAR[0x00998C]))
+#define MCF_FEC_FECRLRFP1 (*(vuint32*)(void*)(&__MBAR[0x009990]))
+#define MCF_FEC_FECRLWFP1 (*(vuint32*)(void*)(&__MBAR[0x009994]))
+#define MCF_FEC_FECRFAR1 (*(vuint32*)(void*)(&__MBAR[0x009998]))
+#define MCF_FEC_FECRFRP1 (*(vuint32*)(void*)(&__MBAR[0x00999C]))
+#define MCF_FEC_FECRFWP1 (*(vuint32*)(void*)(&__MBAR[0x0099A0]))
+#define MCF_FEC_FECTFDR1 (*(vuint32*)(void*)(&__MBAR[0x0099A4]))
+#define MCF_FEC_FECTFSR1 (*(vuint32*)(void*)(&__MBAR[0x0099A8]))
+#define MCF_FEC_FECTFCR1 (*(vuint32*)(void*)(&__MBAR[0x0099AC]))
+#define MCF_FEC_FECTLRFP1 (*(vuint32*)(void*)(&__MBAR[0x0099B0]))
+#define MCF_FEC_FECTLWFP1 (*(vuint32*)(void*)(&__MBAR[0x0099B4]))
+#define MCF_FEC_FECTFAR1 (*(vuint32*)(void*)(&__MBAR[0x0099B8]))
+#define MCF_FEC_FECTFRP1 (*(vuint32*)(void*)(&__MBAR[0x0099BC]))
+#define MCF_FEC_FECTFWP1 (*(vuint32*)(void*)(&__MBAR[0x0099C0]))
+#define MCF_FEC_FRST1 (*(vuint32*)(void*)(&__MBAR[0x0099C4]))
+#define MCF_FEC_CTCWR1 (*(vuint32*)(void*)(&__MBAR[0x0099C8]))
+#define MCF_FEC_RMON_T_DROP1 (*(vuint32*)(void*)(&__MBAR[0x009A00]))
+#define MCF_FEC_RMON_T_PACKETS1 (*(vuint32*)(void*)(&__MBAR[0x009A04]))
+#define MCF_FEC_RMON_T_BC_PKT1 (*(vuint32*)(void*)(&__MBAR[0x009A08]))
+#define MCF_FEC_RMON_T_MC_PKT1 (*(vuint32*)(void*)(&__MBAR[0x009A0C]))
+#define MCF_FEC_RMON_T_CRC_ALIGN1 (*(vuint32*)(void*)(&__MBAR[0x009A10]))
+#define MCF_FEC_RMON_T_UNDERSIZE1 (*(vuint32*)(void*)(&__MBAR[0x009A14]))
+#define MCF_FEC_RMON_T_OVERSIZE1 (*(vuint32*)(void*)(&__MBAR[0x009A18]))
+#define MCF_FEC_RMON_T_FRAG1 (*(vuint32*)(void*)(&__MBAR[0x009A1C]))
+#define MCF_FEC_RMON_T_JAB1 (*(vuint32*)(void*)(&__MBAR[0x009A20]))
+#define MCF_FEC_RMON_T_COL1 (*(vuint32*)(void*)(&__MBAR[0x009A24]))
+#define MCF_FEC_RMON_T_P641 (*(vuint32*)(void*)(&__MBAR[0x009A28]))
+#define MCF_FEC_RMON_T_P65TO1271 (*(vuint32*)(void*)(&__MBAR[0x009A2C]))
+#define MCF_FEC_RMON_T_P128TO2551 (*(vuint32*)(void*)(&__MBAR[0x009A30]))
+#define MCF_FEC_RMON_T_P256TO5111 (*(vuint32*)(void*)(&__MBAR[0x009A34]))
+#define MCF_FEC_RMON_T_P512TO10231 (*(vuint32*)(void*)(&__MBAR[0x009A38]))
+#define MCF_FEC_RMON_T_P1024TO20471 (*(vuint32*)(void*)(&__MBAR[0x009A3C]))
+#define MCF_FEC_RMON_T_P_GTE20481 (*(vuint32*)(void*)(&__MBAR[0x009A40]))
+#define MCF_FEC_RMON_T_OCTETS1 (*(vuint32*)(void*)(&__MBAR[0x009A44]))
+#define MCF_FEC_IEEE_T_DROP1 (*(vuint32*)(void*)(&__MBAR[0x009A48]))
+#define MCF_FEC_IEEE_T_FRAME_OK1 (*(vuint32*)(void*)(&__MBAR[0x009A4C]))
+#define MCF_FEC_IEEE_T_1COL1 (*(vuint32*)(void*)(&__MBAR[0x009A50]))
+#define MCF_FEC_IEEE_T_MCOL1 (*(vuint32*)(void*)(&__MBAR[0x009A54]))
+#define MCF_FEC_IEEE_T_DEF1 (*(vuint32*)(void*)(&__MBAR[0x009A58]))
+#define MCF_FEC_IEEE_T_LCOL1 (*(vuint32*)(void*)(&__MBAR[0x009A5C]))
+#define MCF_FEC_IEEE_T_EXCOL1 (*(vuint32*)(void*)(&__MBAR[0x009A60]))
+#define MCF_FEC_IEEE_T_MACERR1 (*(vuint32*)(void*)(&__MBAR[0x009A64]))
+#define MCF_FEC_IEEE_T_CSERR1 (*(vuint32*)(void*)(&__MBAR[0x009A68]))
+#define MCF_FEC_IEEE_T_SQE1 (*(vuint32*)(void*)(&__MBAR[0x009A6C]))
+#define MCF_FEC_IEEE_T_FDXFC1 (*(vuint32*)(void*)(&__MBAR[0x009A70]))
+#define MCF_FEC_IEEE_T_OCTETS_OK1 (*(vuint32*)(void*)(&__MBAR[0x009A74]))
+#define MCF_FEC_RMON_R_PACKETS1 (*(vuint32*)(void*)(&__MBAR[0x009A84]))
+#define MCF_FEC_RMON_R_BC_PKT1 (*(vuint32*)(void*)(&__MBAR[0x009A88]))
+#define MCF_FEC_RMON_R_MC_PKT1 (*(vuint32*)(void*)(&__MBAR[0x009A8C]))
+#define MCF_FEC_RMON_R_CRC_ALIGN1 (*(vuint32*)(void*)(&__MBAR[0x009A90]))
+#define MCF_FEC_RMON_R_UNDERSIZE1 (*(vuint32*)(void*)(&__MBAR[0x009A94]))
+#define MCF_FEC_RMON_R_OVERSIZE1 (*(vuint32*)(void*)(&__MBAR[0x009A98]))
+#define MCF_FEC_RMON_R_FRAG1 (*(vuint32*)(void*)(&__MBAR[0x009A9C]))
+#define MCF_FEC_RMON_R_JAB1 (*(vuint32*)(void*)(&__MBAR[0x009AA0]))
+#define MCF_FEC_RMON_R_RESVD_01 (*(vuint32*)(void*)(&__MBAR[0x009AA4]))
+#define MCF_FEC_RMON_R_P641 (*(vuint32*)(void*)(&__MBAR[0x009AA8]))
+#define MCF_FEC_RMON_R_P65TO1271 (*(vuint32*)(void*)(&__MBAR[0x009AAC]))
+#define MCF_FEC_RMON_R_P128TO2551 (*(vuint32*)(void*)(&__MBAR[0x009AB0]))
+#define MCF_FEC_RMON_R_P256TO5111 (*(vuint32*)(void*)(&__MBAR[0x009AB4]))
+#define MCF_FEC_RMON_R_512TO10231 (*(vuint32*)(void*)(&__MBAR[0x009AB8]))
+#define MCF_FEC_RMON_R_1024TO20471 (*(vuint32*)(void*)(&__MBAR[0x009ABC]))
+#define MCF_FEC_RMON_R_P_GTE20481 (*(vuint32*)(void*)(&__MBAR[0x009AC0]))
+#define MCF_FEC_RMON_R_OCTETS1 (*(vuint32*)(void*)(&__MBAR[0x009AC4]))
+#define MCF_FEC_IEEE_R_DROP1 (*(vuint32*)(void*)(&__MBAR[0x009AC8]))
+#define MCF_FEC_IEEE_R_FRAME_OK1 (*(vuint32*)(void*)(&__MBAR[0x009ACC]))
+#define MCF_FEC_IEEE_R_CRC1 (*(vuint32*)(void*)(&__MBAR[0x009AD0]))
+#define MCF_FEC_IEEE_R_ALIGN1 (*(vuint32*)(void*)(&__MBAR[0x009AD4]))
+#define MCF_FEC_IEEE_R_MACERR1 (*(vuint32*)(void*)(&__MBAR[0x009AD8]))
+#define MCF_FEC_IEEE_R_FDXFC1 (*(vuint32*)(void*)(&__MBAR[0x009ADC]))
+#define MCF_FEC_IEEE_R_OCTETS_OK1 (*(vuint32*)(void*)(&__MBAR[0x009AE0]))
+#define MCF_FEC_EIR(x) (*(vuint32*)(void*)(&__MBAR[0x009004+((x)*0x800)]))
+#define MCF_FEC_EIMR(x) (*(vuint32*)(void*)(&__MBAR[0x009008+((x)*0x800)]))
+#define MCF_FEC_ECR(x) (*(vuint32*)(void*)(&__MBAR[0x009024+((x)*0x800)]))
+#define MCF_FEC_MMFR(x) (*(vuint32*)(void*)(&__MBAR[0x009040+((x)*0x800)]))
+#define MCF_FEC_MSCR(x) (*(vuint32*)(void*)(&__MBAR[0x009044+((x)*0x800)]))
+#define MCF_FEC_MIBC(x) (*(vuint32*)(void*)(&__MBAR[0x009064+((x)*0x800)]))
+#define MCF_FEC_RCR(x) (*(vuint32*)(void*)(&__MBAR[0x009084+((x)*0x800)]))
+#define MCF_FEC_R_HASH(x) (*(vuint32*)(void*)(&__MBAR[0x009088+((x)*0x800)]))
+#define MCF_FEC_TCR(x) (*(vuint32*)(void*)(&__MBAR[0x0090C4+((x)*0x800)]))
+#define MCF_FEC_PALR(x) (*(vuint32*)(void*)(&__MBAR[0x0090E4+((x)*0x800)]))
+#define MCF_FEC_PAUR(x) (*(vuint32*)(void*)(&__MBAR[0x0090E8+((x)*0x800)]))
+#define MCF_FEC_OPD(x) (*(vuint32*)(void*)(&__MBAR[0x0090EC+((x)*0x800)]))
+#define MCF_FEC_IAUR(x) (*(vuint32*)(void*)(&__MBAR[0x009118+((x)*0x800)]))
+#define MCF_FEC_IALR(x) (*(vuint32*)(void*)(&__MBAR[0x00911C+((x)*0x800)]))
+#define MCF_FEC_GAUR(x) (*(vuint32*)(void*)(&__MBAR[0x009120+((x)*0x800)]))
+#define MCF_FEC_GALR(x) (*(vuint32*)(void*)(&__MBAR[0x009124+((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x) (*(vuint32*)(void*)(&__MBAR[0x009144+((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x) (*(vuint32*)(void*)(&__MBAR[0x009184+((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x) (*(vuint32*)(void*)(&__MBAR[0x009188+((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x) (*(vuint32*)(void*)(&__MBAR[0x00918C+((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(void*)(&__MBAR[0x009190+((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(void*)(&__MBAR[0x009194+((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x) (*(vuint32*)(void*)(&__MBAR[0x009198+((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x) (*(vuint32*)(void*)(&__MBAR[0x00919C+((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x) (*(vuint32*)(void*)(&__MBAR[0x0091A0+((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x) (*(vuint32*)(void*)(&__MBAR[0x0091A4+((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x) (*(vuint32*)(void*)(&__MBAR[0x0091A8+((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x) (*(vuint32*)(void*)(&__MBAR[0x0091AC+((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(void*)(&__MBAR[0x0091B0+((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(void*)(&__MBAR[0x0091B4+((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x) (*(vuint32*)(void*)(&__MBAR[0x0091B8+((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x) (*(vuint32*)(void*)(&__MBAR[0x0091BC+((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x) (*(vuint32*)(void*)(&__MBAR[0x0091C0+((x)*0x800)]))
+#define MCF_FEC_FRST(x) (*(vuint32*)(void*)(&__MBAR[0x0091C4+((x)*0x800)]))
+#define MCF_FEC_CTCWR(x) (*(vuint32*)(void*)(&__MBAR[0x0091C8+((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(void*)(&__MBAR[0x009200+((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(void*)(&__MBAR[0x009204+((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(void*)(&__MBAR[0x009208+((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(void*)(&__MBAR[0x00920C+((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(void*)(&__MBAR[0x009210+((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(void*)(&__MBAR[0x009214+((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(void*)(&__MBAR[0x009218+((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(void*)(&__MBAR[0x00921C+((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(void*)(&__MBAR[0x009220+((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(void*)(&__MBAR[0x009224+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(void*)(&__MBAR[0x009228+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(void*)(&__MBAR[0x00922C+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(void*)(&__MBAR[0x009230+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(void*)(&__MBAR[0x009234+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(void*)(&__MBAR[0x009238+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(void*)(&__MBAR[0x00923C+((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(void*)(&__MBAR[0x009240+((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(void*)(&__MBAR[0x009244+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(void*)(&__MBAR[0x009248+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(void*)(&__MBAR[0x00924C+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(void*)(&__MBAR[0x009250+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(void*)(&__MBAR[0x009254+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(void*)(&__MBAR[0x009258+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(void*)(&__MBAR[0x00925C+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(void*)(&__MBAR[0x009260+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(void*)(&__MBAR[0x009264+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(void*)(&__MBAR[0x009268+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(void*)(&__MBAR[0x00926C+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(void*)(&__MBAR[0x009270+((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(void*)(&__MBAR[0x009274+((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(void*)(&__MBAR[0x009284+((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(void*)(&__MBAR[0x009288+((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(void*)(&__MBAR[0x00928C+((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(void*)(&__MBAR[0x009290+((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(void*)(&__MBAR[0x009294+((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(void*)(&__MBAR[0x009298+((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(void*)(&__MBAR[0x00929C+((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(void*)(&__MBAR[0x0092A0+((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(void*)(&__MBAR[0x0092A4+((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(void*)(&__MBAR[0x0092A8+((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(void*)(&__MBAR[0x0092AC+((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(void*)(&__MBAR[0x0092B0+((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(void*)(&__MBAR[0x0092B4+((x)*0x800)]))
+#define MCF_FEC_RMON_R_512TO1023(x) (*(vuint32*)(void*)(&__MBAR[0x0092B8+((x)*0x800)]))
+#define MCF_FEC_RMON_R_1024TO2047(x) (*(vuint32*)(void*)(&__MBAR[0x0092BC+((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(void*)(&__MBAR[0x0092C0+((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(void*)(&__MBAR[0x0092C4+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(void*)(&__MBAR[0x0092C8+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(void*)(&__MBAR[0x0092CC+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(void*)(&__MBAR[0x0092D0+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(void*)(&__MBAR[0x0092D4+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(void*)(&__MBAR[0x0092D8+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(void*)(&__MBAR[0x0092DC+((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(void*)(&__MBAR[0x0092E0+((x)*0x800)]))
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR (0x00020000)
+#define MCF_FEC_EIR_XFERR (0x00040000)
+#define MCF_FEC_EIR_XFUN (0x00080000)
+#define MCF_FEC_EIR_RL (0x00100000)
+#define MCF_FEC_EIR_LC (0x00200000)
+#define MCF_FEC_EIR_MII (0x00800000)
+#define MCF_FEC_EIR_TXF (0x08000000)
+#define MCF_FEC_EIR_GRA (0x10000000)
+#define MCF_FEC_EIR_BABT (0x20000000)
+#define MCF_FEC_EIR_BABR (0x40000000)
+#define MCF_FEC_EIR_HBERR (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR (0x00020000)
+#define MCF_FEC_EIMR_XFERR (0x00040000)
+#define MCF_FEC_EIMR_XFUN (0x00080000)
+#define MCF_FEC_EIMR_RL (0x00100000)
+#define MCF_FEC_EIMR_LC (0x00200000)
+#define MCF_FEC_EIMR_MII (0x00800000)
+#define MCF_FEC_EIMR_TXF (0x08000000)
+#define MCF_FEC_EIMR_GRA (0x10000000)
+#define MCF_FEC_EIMR_BABT (0x20000000)
+#define MCF_FEC_EIMR_BABR (0x40000000)
+#define MCF_FEC_EIMR_HBERR (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL (0x00000000)
+#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET (0x00000001)
+#define MCF_FEC_ECR_ETHER_EN (0x00000002)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
+#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
+#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
+#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
+#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
+#define MCF_FEC_MMFR_ST_01 (0x40000000)
+#define MCF_FEC_MMFR_OP_READ (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
+#define MCF_FEC_MMFR_TA_10 (0x00020000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
+#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<1)
+#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<1)
+#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<1)
+#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP (0x00000001)
+#define MCF_FEC_RCR_DRT (0x00000002)
+#define MCF_FEC_RCR_MII_MODE (0x00000004)
+#define MCF_FEC_RCR_PROM (0x00000008)
+#define MCF_FEC_RCR_BC_REJ (0x00000010)
+#define MCF_FEC_RCR_FCE (0x00000020)
+#define MCF_FEC_RCR_MAX_FL(x) (((uint32)(x)&0x000007FF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_R_HASH */
+#define MCF_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24)
+#define MCF_FEC_R_HASH_MULTCAST (0x40000000)
+#define MCF_FEC_R_HASH_FCE_DC (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS (0x00000001)
+#define MCF_FEC_TCR_HBC (0x00000002)
+#define MCF_FEC_TCR_FDEN (0x00000004)
+#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
+#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
+
+/* Bit definitions and macros for MCF_FEC_PAUR */
+#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64 (0x00000000)
+#define MCF_FEC_FECTFWR_X_WMRK_128 (0x00000001)
+#define MCF_FEC_FECTFWR_X_WMRK_192 (0x00000002)
+#define MCF_FEC_FECTFWR_X_WMRK_256 (0x00000003)
+#define MCF_FEC_FECTFWR_X_WMRK_320 (0x00000004)
+#define MCF_FEC_FECTFWR_X_WMRK_384 (0x00000005)
+#define MCF_FEC_FECTFWR_X_WMRK_448 (0x00000006)
+#define MCF_FEC_FECTFWR_X_WMRK_512 (0x00000007)
+#define MCF_FEC_FECTFWR_X_WMRK_576 (0x00000008)
+#define MCF_FEC_FECTFWR_X_WMRK_640 (0x00000009)
+#define MCF_FEC_FECTFWR_X_WMRK_704 (0x0000000A)
+#define MCF_FEC_FECTFWR_X_WMRK_768 (0x0000000B)
+#define MCF_FEC_FECTFWR_X_WMRK_832 (0x0000000C)
+#define MCF_FEC_FECTFWR_X_WMRK_896 (0x0000000D)
+#define MCF_FEC_FECTFWR_X_WMRK_960 (0x0000000E)
+#define MCF_FEC_FECTFWR_X_WMRK_1024 (0x0000000F)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_ADDR0 ((void*)(&__MBAR[0x009184]))
+#define MCF_FEC_FECRFDR_ADDR1 ((void*)(&__MBAR[0x009984]))
+#define MCF_FEC_FECRFDR_ADDR(x) ((void*)(&__MBAR[0x009184+(0x800*x)]))
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT (0x00010000)
+#define MCF_FEC_FECRFSR_ALARM (0x00020000)
+#define MCF_FEC_FECRFSR_FU (0x00040000)
+#define MCF_FEC_FECRFSR_FR (0x00080000)
+#define MCF_FEC_FECRFSR_OF (0x00100000)
+#define MCF_FEC_FECRFSR_UF (0x00200000)
+#define MCF_FEC_FECRFSR_RXW (0x00400000)
+#define MCF_FEC_FECRFSR_FAE (0x00800000)
+#define MCF_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24)
+#define MCF_FEC_FECRFSR_IP (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK (0x00080000)
+#define MCF_FEC_FECRFCR_UF_MSK (0x00100000)
+#define MCF_FEC_FECRFCR_RXW_MSK (0x00200000)
+#define MCF_FEC_FECRFCR_FAE_MSK (0x00400000)
+#define MCF_FEC_FECRFCR_IP_MSK (0x00800000)
+#define MCF_FEC_FECRFCR_GR(x) (((uint32)(x)&0x00000007)<<24)
+#define MCF_FEC_FECRFCR_FRM (0x08000000)
+#define MCF_FEC_FECRFCR_TIMER (0x10000000)
+#define MCF_FEC_FECRFCR_WFR (0x20000000)
+#define MCF_FEC_FECRFCR_WCTL (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_TFCW_TC (0x04000000)
+#define MCF_FEC_FECTFDR_TFCW_ABC (0x02000000)
+#define MCF_FEC_FECTFDR_ADDR0 ((void*)(&__MBAR[0x0091A4]))
+#define MCF_FEC_FECTFDR_ADDR1 ((void*)(&__MBAR[0x0099A4]))
+#define MCF_FEC_FECTFDR_ADDR(x) ((void*)(&__MBAR[0x0091A4+(0x800*x)]))
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT (0x00010000)
+#define MCF_FEC_FECTFSR_ALARM (0x00020000)
+#define MCF_FEC_FECTFSR_FU (0x00040000)
+#define MCF_FEC_FECTFSR_FR (0x00080000)
+#define MCF_FEC_FECTFSR_OF (0x00100000)
+#define MCF_FEC_FECTFSR_UP (0x00200000)
+#define MCF_FEC_FECTFSR_FAE (0x00800000)
+#define MCF_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24)
+#define MCF_FEC_FECTFSR_TXW (0x40000000)
+#define MCF_FEC_FECTFSR_IP (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED (0x00200000)
+#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000)
+#define MCF_FEC_FECTFCR_TXW_MSK (0x00240000)
+#define MCF_FEC_FECTFCR_OF_MSK (0x00280000)
+#define MCF_FEC_FECTFCR_UF_MSK (0x00300000)
+#define MCF_FEC_FECTFCR_FAE_MSK (0x00600000)
+#define MCF_FEC_FECTFCR_IP_MSK (0x00A00000)
+#define MCF_FEC_FECTFCR_GR(x) (((uint32)(x)&0x00000007)<<24|0x00200000)
+#define MCF_FEC_FECTFCR_FRM (0x08200000)
+#define MCF_FEC_FECTFCR_TIMER (0x10200000)
+#define MCF_FEC_FECTFCR_WFR (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FRST */
+#define MCF_FEC_FRST_RST_CTL (0x01000000)
+#define MCF_FEC_FRST_SW_RST (0x02000000)
+
+/* Bit definitions and macros for MCF_FEC_CTCWR */
+#define MCF_FEC_CTCWR_TFCW (0x01000000)
+#define MCF_FEC_CTCWR_CRC (0x02000000)
+
+/********************************************************************/
+
+#endif /* __MCF548X_FEC_H__ */
diff -aurN -x CVS ./xif.orig//fec/platform/mcf548x_gpio.h ./xif/fec/platform/mcf548x_gpio.h
--- ./xif.orig//fec/platform/mcf548x_gpio.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/mcf548x_gpio.h 2004-06-27 15:57:20.000000000 +0200
@@ -0,0 +1,696 @@
+/*
+ * File: mcf548x_gpio.h
+ * Purpose: Register and bit definitions for the MCF548X
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __MCF548X_GPIO_H__
+#define __MCF548X_GPIO_H__
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(void*)(&__MBAR[0x000A00]))
+#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(void*)(&__MBAR[0x000A01]))
+#define MCF_GPIO_PODR_DMA (*(vuint8 *)(void*)(&__MBAR[0x000A02]))
+#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(void*)(&__MBAR[0x000A04]))
+#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(void*)(&__MBAR[0x000A05]))
+#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(void*)(&__MBAR[0x000A06]))
+#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(void*)(&__MBAR[0x000A07]))
+#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__MBAR[0x000A08]))
+#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(void*)(&__MBAR[0x000A09]))
+#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(void*)(&__MBAR[0x000A0A]))
+#define MCF_GPIO_PODR_PSC3PSC2 (*(vuint8 *)(void*)(&__MBAR[0x000A0C]))
+#define MCF_GPIO_PODR_PSC1PSC0 (*(vuint8 *)(void*)(&__MBAR[0x000A0D]))
+#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(void*)(&__MBAR[0x000A0E]))
+#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(void*)(&__MBAR[0x000A10]))
+#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(void*)(&__MBAR[0x000A11]))
+#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(void*)(&__MBAR[0x000A12]))
+#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(void*)(&__MBAR[0x000A14]))
+#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(void*)(&__MBAR[0x000A15]))
+#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(void*)(&__MBAR[0x000A16]))
+#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(void*)(&__MBAR[0x000A17]))
+#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__MBAR[0x000A18]))
+#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(void*)(&__MBAR[0x000A19]))
+#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(void*)(&__MBAR[0x000A1A]))
+#define MCF_GPIO_PDDR_PSC3PSC2 (*(vuint8 *)(void*)(&__MBAR[0x000A1C]))
+#define MCF_GPIO_PDDR_PSC1PSC0 (*(vuint8 *)(void*)(&__MBAR[0x000A1D]))
+#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(void*)(&__MBAR[0x000A1E]))
+#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(void*)(&__MBAR[0x000A20]))
+#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(void*)(&__MBAR[0x000A21]))
+#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(void*)(&__MBAR[0x000A22]))
+#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(void*)(&__MBAR[0x000A24]))
+#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(void*)(&__MBAR[0x000A25]))
+#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(void*)(&__MBAR[0x000A26]))
+#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(void*)(&__MBAR[0x000A27]))
+#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__MBAR[0x000A28]))
+#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(void*)(&__MBAR[0x000A29]))
+#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(void*)(&__MBAR[0x000A2A]))
+#define MCF_GPIO_PPDSDR_PSC3PSC2 (*(vuint8 *)(void*)(&__MBAR[0x000A2C]))
+#define MCF_GPIO_PPDSDR_PSC1PSC0 (*(vuint8 *)(void*)(&__MBAR[0x000A2D]))
+#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(void*)(&__MBAR[0x000A2E]))
+#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(void*)(&__MBAR[0x000A30]))
+#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(void*)(&__MBAR[0x000A31]))
+#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(void*)(&__MBAR[0x000A32]))
+#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(void*)(&__MBAR[0x000A34]))
+#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(void*)(&__MBAR[0x000A35]))
+#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(void*)(&__MBAR[0x000A36]))
+#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(void*)(&__MBAR[0x000A37]))
+#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__MBAR[0x000A38]))
+#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(void*)(&__MBAR[0x000A39]))
+#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(void*)(&__MBAR[0x000A3A]))
+#define MCF_GPIO_PCLRR_PSC3PSC2 (*(vuint8 *)(void*)(&__MBAR[0x000A3C]))
+#define MCF_GPIO_PCLRR_PSC1PSC0 (*(vuint8 *)(void*)(&__MBAR[0x000A3D]))
+#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(void*)(&__MBAR[0x000A3E]))
+#define MCF_GPIO_PAR_FBCTL (*(vuint16*)(void*)(&__MBAR[0x000A40]))
+#define MCF_GPIO_PAR_FBCS (*(vuint8 *)(void*)(&__MBAR[0x000A42]))
+#define MCF_GPIO_PAR_DMA (*(vuint8 *)(void*)(&__MBAR[0x000A43]))
+#define MCF_GPIO_PAR_FECI2CIRQ (*(vuint16*)(void*)(&__MBAR[0x000A44]))
+#define MCF_GPIO_PAR_PCIBG (*(vuint16*)(void*)(&__MBAR[0x000A48]))
+#define MCF_GPIO_PAR_PCIBR (*(vuint16*)(void*)(&__MBAR[0x000A4A]))
+#define MCF_GPIO_PAR_PSC3 (*(vuint8 *)(void*)(&__MBAR[0x000A4C]))
+#define MCF_GPIO_PAR_PSC2 (*(vuint8 *)(void*)(&__MBAR[0x000A4D]))
+#define MCF_GPIO_PAR_PSC1 (*(vuint8 *)(void*)(&__MBAR[0x000A4E]))
+#define MCF_GPIO_PAR_PSC0 (*(vuint8 *)(void*)(&__MBAR[0x000A4F]))
+#define MCF_GPIO_PAR_DSPI (*(vuint16*)(void*)(&__MBAR[0x000A50]))
+#define MCF_GPIO_PAR_TIMER (*(vuint8 *)(void*)(&__MBAR[0x000A52]))
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x02)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x04)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x08)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x01)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x02)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x04)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x01)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x02)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x04)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x08)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x01)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x02)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x04)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08)
+#define MCF_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01)
+#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08)
+#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04)
+#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08)
+#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08)
+#define MCF_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
+#define MCF_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01)
+#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02)
+#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04)
+#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08)
+#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
+#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
+#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004)
+#define MCF_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040)
+#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100)
+#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400)
+#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000)
+#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000)
+#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0)
+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2)
+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3)
+#define MCF_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000)
+#define MCF_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020)
+#define MCF_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
+#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02)
+#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04)
+#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08)
+#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10)
+#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
+#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0)
+#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2)
+#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3)
+#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0)
+#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2)
+#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080)
+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
+#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04)
+#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08)
+#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80)
+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0)
+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30)
+#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
+#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04)
+#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08)
+#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80)
+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0)
+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10)
+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
+#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
+#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
+#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
+#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
+#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
+#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
+#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
+#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
+#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
+#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
+#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
+#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
+#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
+#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
+#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
+#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
+#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
+#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
+#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
+#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
+#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
+#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
+#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
+
+/********************************************************************/
+
+#endif /* __MCF548X_GPIO_H__ */
diff -aurN -x CVS ./xif.orig//fec/platform/mcf548x_intc.h ./xif/fec/platform/mcf548x_intc.h
--- ./xif.orig//fec/platform/mcf548x_intc.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/mcf548x_intc.h 2011-10-13 23:04:09.000000000 +0200
@@ -0,0 +1,317 @@
+/*
+ * File: mcf548x_intc.h
+ * Purpose: Register and bit definitions for the MCF548X
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __MCF548X_INTC_H__
+#define __MCF548X_INTC_H__
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH (*(vuint32*)(void*)(&__MBAR[0x000700]))
+#define MCF_INTC_IPRL (*(vuint32*)(void*)(&__MBAR[0x000704]))
+#define MCF_INTC_IMRH (*(vuint32*)(void*)(&__MBAR[0x000708]))
+#define MCF_INTC_IMRL (*(vuint32*)(void*)(&__MBAR[0x00070C]))
+#define MCF_INTC_INTFRCH (*(vuint32*)(void*)(&__MBAR[0x000710]))
+#define MCF_INTC_INTFRCL (*(vuint32*)(void*)(&__MBAR[0x000714]))
+#define MCF_INTC_IRLR (*(vuint8 *)(void*)(&__MBAR[0x000718]))
+#define MCF_INTC_IACKLPR (*(vuint8 *)(void*)(&__MBAR[0x000719]))
+#define MCF_INTC_ICR0 (*(vuint8 *)(void*)(&__MBAR[0x000740]))
+#define MCF_INTC_ICR1 (*(vuint8 *)(void*)(&__MBAR[0x000741]))
+#define MCF_INTC_ICR2 (*(vuint8 *)(void*)(&__MBAR[0x000742]))
+#define MCF_INTC_ICR3 (*(vuint8 *)(void*)(&__MBAR[0x000743]))
+#define MCF_INTC_ICR4 (*(vuint8 *)(void*)(&__MBAR[0x000744]))
+#define MCF_INTC_ICR5 (*(vuint8 *)(void*)(&__MBAR[0x000745]))
+#define MCF_INTC_ICR6 (*(vuint8 *)(void*)(&__MBAR[0x000746]))
+#define MCF_INTC_ICR7 (*(vuint8 *)(void*)(&__MBAR[0x000747]))
+#define MCF_INTC_ICR8 (*(vuint8 *)(void*)(&__MBAR[0x000748]))
+#define MCF_INTC_ICR9 (*(vuint8 *)(void*)(&__MBAR[0x000749]))
+#define MCF_INTC_ICR10 (*(vuint8 *)(void*)(&__MBAR[0x00074A]))
+#define MCF_INTC_ICR11 (*(vuint8 *)(void*)(&__MBAR[0x00074B]))
+#define MCF_INTC_ICR12 (*(vuint8 *)(void*)(&__MBAR[0x00074C]))
+#define MCF_INTC_ICR13 (*(vuint8 *)(void*)(&__MBAR[0x00074D]))
+#define MCF_INTC_ICR14 (*(vuint8 *)(void*)(&__MBAR[0x00074E]))
+#define MCF_INTC_ICR15 (*(vuint8 *)(void*)(&__MBAR[0x00074F]))
+#define MCF_INTC_ICR16 (*(vuint8 *)(void*)(&__MBAR[0x000750]))
+#define MCF_INTC_ICR17 (*(vuint8 *)(void*)(&__MBAR[0x000751]))
+#define MCF_INTC_ICR18 (*(vuint8 *)(void*)(&__MBAR[0x000752]))
+#define MCF_INTC_ICR19 (*(vuint8 *)(void*)(&__MBAR[0x000753]))
+#define MCF_INTC_ICR20 (*(vuint8 *)(void*)(&__MBAR[0x000754]))
+#define MCF_INTC_ICR21 (*(vuint8 *)(void*)(&__MBAR[0x000755]))
+#define MCF_INTC_ICR22 (*(vuint8 *)(void*)(&__MBAR[0x000756]))
+#define MCF_INTC_ICR23 (*(vuint8 *)(void*)(&__MBAR[0x000757]))
+#define MCF_INTC_ICR24 (*(vuint8 *)(void*)(&__MBAR[0x000758]))
+#define MCF_INTC_ICR25 (*(vuint8 *)(void*)(&__MBAR[0x000759]))
+#define MCF_INTC_ICR26 (*(vuint8 *)(void*)(&__MBAR[0x00075A]))
+#define MCF_INTC_ICR27 (*(vuint8 *)(void*)(&__MBAR[0x00075B]))
+#define MCF_INTC_ICR28 (*(vuint8 *)(void*)(&__MBAR[0x00075C]))
+#define MCF_INTC_ICR29 (*(vuint8 *)(void*)(&__MBAR[0x00075D]))
+#define MCF_INTC_ICR30 (*(vuint8 *)(void*)(&__MBAR[0x00075E]))
+#define MCF_INTC_ICR31 (*(vuint8 *)(void*)(&__MBAR[0x00075F]))
+#define MCF_INTC_ICR32 (*(vuint8 *)(void*)(&__MBAR[0x000760]))
+#define MCF_INTC_ICR33 (*(vuint8 *)(void*)(&__MBAR[0x000761]))
+#define MCF_INTC_ICR34 (*(vuint8 *)(void*)(&__MBAR[0x000762]))
+#define MCF_INTC_ICR35 (*(vuint8 *)(void*)(&__MBAR[0x000763]))
+#define MCF_INTC_ICR36 (*(vuint8 *)(void*)(&__MBAR[0x000764]))
+#define MCF_INTC_ICR37 (*(vuint8 *)(void*)(&__MBAR[0x000765]))
+#define MCF_INTC_ICR38 (*(vuint8 *)(void*)(&__MBAR[0x000766]))
+#define MCF_INTC_ICR39 (*(vuint8 *)(void*)(&__MBAR[0x000767]))
+#define MCF_INTC_ICR40 (*(vuint8 *)(void*)(&__MBAR[0x000768]))
+#define MCF_INTC_ICR41 (*(vuint8 *)(void*)(&__MBAR[0x000769]))
+#define MCF_INTC_ICR42 (*(vuint8 *)(void*)(&__MBAR[0x00076A]))
+#define MCF_INTC_ICR43 (*(vuint8 *)(void*)(&__MBAR[0x00076B]))
+#define MCF_INTC_ICR44 (*(vuint8 *)(void*)(&__MBAR[0x00076C]))
+#define MCF_INTC_ICR45 (*(vuint8 *)(void*)(&__MBAR[0x00076D]))
+#define MCF_INTC_ICR46 (*(vuint8 *)(void*)(&__MBAR[0x00076E]))
+#define MCF_INTC_ICR47 (*(vuint8 *)(void*)(&__MBAR[0x00076F]))
+#define MCF_INTC_ICR48 (*(vuint8 *)(void*)(&__MBAR[0x000770]))
+#define MCF_INTC_ICR49 (*(vuint8 *)(void*)(&__MBAR[0x000771]))
+#define MCF_INTC_ICR50 (*(vuint8 *)(void*)(&__MBAR[0x000772]))
+#define MCF_INTC_ICR51 (*(vuint8 *)(void*)(&__MBAR[0x000773]))
+#define MCF_INTC_ICR52 (*(vuint8 *)(void*)(&__MBAR[0x000774]))
+#define MCF_INTC_ICR53 (*(vuint8 *)(void*)(&__MBAR[0x000775]))
+#define MCF_INTC_ICR54 (*(vuint8 *)(void*)(&__MBAR[0x000776]))
+#define MCF_INTC_ICR55 (*(vuint8 *)(void*)(&__MBAR[0x000777]))
+#define MCF_INTC_ICR56 (*(vuint8 *)(void*)(&__MBAR[0x000778]))
+#define MCF_INTC_ICR57 (*(vuint8 *)(void*)(&__MBAR[0x000779]))
+#define MCF_INTC_ICR58 (*(vuint8 *)(void*)(&__MBAR[0x00077A]))
+#define MCF_INTC_ICR59 (*(vuint8 *)(void*)(&__MBAR[0x00077B]))
+#define MCF_INTC_ICR60 (*(vuint8 *)(void*)(&__MBAR[0x00077C]))
+#define MCF_INTC_ICR61 (*(vuint8 *)(void*)(&__MBAR[0x00077D]))
+#define MCF_INTC_ICR62 (*(vuint8 *)(void*)(&__MBAR[0x00077E]))
+#define MCF_INTC_ICR63 (*(vuint8 *)(void*)(&__MBAR[0x00077F]))
+#define MCF_INTC_ICRn(x) (*(vuint8 *)(void*)(&__MBAR[0x000740+((x)*0x001)]))
+#define MCF_INTC_SWIACK (*(vuint8 *)(void*)(&__MBAR[0x0007E0]))
+#define MCF_INTC_L1IACK (*(vuint8 *)(void*)(&__MBAR[0x0007E4]))
+#define MCF_INTC_L2IACK (*(vuint8 *)(void*)(&__MBAR[0x0007E8]))
+#define MCF_INTC_L3IACK (*(vuint8 *)(void*)(&__MBAR[0x0007EC]))
+#define MCF_INTC_L4IACK (*(vuint8 *)(void*)(&__MBAR[0x0007F0]))
+#define MCF_INTC_L5IACK (*(vuint8 *)(void*)(&__MBAR[0x0007F4]))
+#define MCF_INTC_L6IACK (*(vuint8 *)(void*)(&__MBAR[0x0007F8]))
+#define MCF_INTC_L7IACK (*(vuint8 *)(void*)(&__MBAR[0x0007FC]))
+#define MCF_INTC_LnIACK(x) (*(vuint8 *)(void*)(&__MBAR[0x0007E4+((x)*0x004)]))
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32 (0x00000001)
+#define MCF_INTC_IPRH_INT33 (0x00000002)
+#define MCF_INTC_IPRH_INT34 (0x00000004)
+#define MCF_INTC_IPRH_INT35 (0x00000008)
+#define MCF_INTC_IPRH_INT36 (0x00000010)
+#define MCF_INTC_IPRH_INT37 (0x00000020)
+#define MCF_INTC_IPRH_INT38 (0x00000040)
+#define MCF_INTC_IPRH_INT39 (0x00000080)
+#define MCF_INTC_IPRH_INT40 (0x00000100)
+#define MCF_INTC_IPRH_INT41 (0x00000200)
+#define MCF_INTC_IPRH_INT42 (0x00000400)
+#define MCF_INTC_IPRH_INT43 (0x00000800)
+#define MCF_INTC_IPRH_INT44 (0x00001000)
+#define MCF_INTC_IPRH_INT45 (0x00002000)
+#define MCF_INTC_IPRH_INT46 (0x00004000)
+#define MCF_INTC_IPRH_INT47 (0x00008000)
+#define MCF_INTC_IPRH_INT48 (0x00010000)
+#define MCF_INTC_IPRH_INT49 (0x00020000)
+#define MCF_INTC_IPRH_INT50 (0x00040000)
+#define MCF_INTC_IPRH_INT51 (0x00080000)
+#define MCF_INTC_IPRH_INT52 (0x00100000)
+#define MCF_INTC_IPRH_INT53 (0x00200000)
+#define MCF_INTC_IPRH_INT54 (0x00400000)
+#define MCF_INTC_IPRH_INT55 (0x00800000)
+#define MCF_INTC_IPRH_INT56 (0x01000000)
+#define MCF_INTC_IPRH_INT57 (0x02000000)
+#define MCF_INTC_IPRH_INT58 (0x04000000)
+#define MCF_INTC_IPRH_INT59 (0x08000000)
+#define MCF_INTC_IPRH_INT60 (0x10000000)
+#define MCF_INTC_IPRH_INT61 (0x20000000)
+#define MCF_INTC_IPRH_INT62 (0x40000000)
+#define MCF_INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1 (0x00000002)
+#define MCF_INTC_IPRL_INT2 (0x00000004)
+#define MCF_INTC_IPRL_INT3 (0x00000008)
+#define MCF_INTC_IPRL_INT4 (0x00000010)
+#define MCF_INTC_IPRL_INT5 (0x00000020)
+#define MCF_INTC_IPRL_INT6 (0x00000040)
+#define MCF_INTC_IPRL_INT7 (0x00000080)
+#define MCF_INTC_IPRL_INT8 (0x00000100)
+#define MCF_INTC_IPRL_INT9 (0x00000200)
+#define MCF_INTC_IPRL_INT10 (0x00000400)
+#define MCF_INTC_IPRL_INT11 (0x00000800)
+#define MCF_INTC_IPRL_INT12 (0x00001000)
+#define MCF_INTC_IPRL_INT13 (0x00002000)
+#define MCF_INTC_IPRL_INT14 (0x00004000)
+#define MCF_INTC_IPRL_INT15 (0x00008000)
+#define MCF_INTC_IPRL_INT16 (0x00010000)
+#define MCF_INTC_IPRL_INT17 (0x00020000)
+#define MCF_INTC_IPRL_INT18 (0x00040000)
+#define MCF_INTC_IPRL_INT19 (0x00080000)
+#define MCF_INTC_IPRL_INT20 (0x00100000)
+#define MCF_INTC_IPRL_INT21 (0x00200000)
+#define MCF_INTC_IPRL_INT22 (0x00400000)
+#define MCF_INTC_IPRL_INT23 (0x00800000)
+#define MCF_INTC_IPRL_INT24 (0x01000000)
+#define MCF_INTC_IPRL_INT25 (0x02000000)
+#define MCF_INTC_IPRL_INT26 (0x04000000)
+#define MCF_INTC_IPRL_INT27 (0x08000000)
+#define MCF_INTC_IPRL_INT28 (0x10000000)
+#define MCF_INTC_IPRL_INT29 (0x20000000)
+#define MCF_INTC_IPRL_INT30 (0x40000000)
+#define MCF_INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
+#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
+#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
+#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
+#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
+#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
+#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
+#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
+#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
+#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
+#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
+#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
+#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
+#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
+#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
+#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
+#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
+#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
+#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
+#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
+#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
+#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
+#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
+#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
+#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
+#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
+#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
+#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL (0x00000001)
+#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
+#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
+#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
+#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
+#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
+#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
+#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
+#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
+#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
+#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
+#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
+#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
+#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
+#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
+#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
+#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
+#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
+#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
+#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
+#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
+#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
+#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
+#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
+#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
+#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
+#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
+#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
+#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
+#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
+#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
+#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
+#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
+#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
+#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
+#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
+#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
+#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
+#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
+#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
+#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
+#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
+#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
+#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
+#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
+#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
+#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
+#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
+#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
+#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
+#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
+#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
+#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
+#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
+#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
+#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
+#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
+#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
+#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
+#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
+#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
+#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
+#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
+#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
+#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
+#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
+#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
+#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
+#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
+#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
+#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
+#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
+#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
+#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
+#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
+#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
+#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
+#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
+#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
+#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
+#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
+
+/* Bit definitions and macros for MCF_INTC_ICRn */
+#define MCF_INTC_ICRn_IP(x) (((x)&0x07)<<0)
+#define MCF_INTC_ICRn_IL(x) (((x)&0x07)<<3)
+
+/********************************************************************/
+
+#endif /* __MCF548X_INTC_H__ */
diff -aurN -x CVS ./xif.orig//fec/platform/types.h ./xif/fec/platform/types.h
--- ./xif.orig//fec/platform/types.h 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/platform/types.h 2011-10-11 20:19:40.000000000 +0200
@@ -0,0 +1,22 @@
+#ifndef TYPES_H
+#define TYPES_H
+
+typedef unsigned char uint8; /* 8 bits */
+typedef unsigned short int uint16; /* 16 bits */
+typedef unsigned long int uint32; /* 32 bits */
+
+typedef char int8; /* 8 bits */
+typedef short int int16; /* 16 bits */
+typedef int int32; /* 32 bits */
+
+typedef volatile uint8 vuint8; /* 8 bits */
+typedef volatile uint16 vuint16; /* 16 bits */
+typedef volatile uint32 vuint32; /* 32 bits */
+
+#define ADDRESS uint32
+#define INSTRUCTION uint16
+#define ILLEGAL 0x4AFC
+#define CPU_WORD_SIZE 16
+
+
+#endif
diff -aurN -x CVS ./xif.orig//fec/README ./xif/fec/README
--- ./xif.orig//fec/README 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/README 2011-11-10 22:58:46.000000000 +0100
@@ -0,0 +1,70 @@
+fec.xif
+==========
+
+The MiNT-Net xif driver for Firebee onboard ethernet interface,
+based on Freescale DMA API.
+
+
+Installation and usage
+======================
+
+Install MiNT-Net and copy the fecdma.xif into your mint folder.
+Then configure the eth0 interface as usual.
+
+Bring up the network interface and assign an specific IP to it:
+ifconfig eth0 addr 192.168.220.101
+
+To add an route to an specific host within you network:
+route add 192.168.220.99 eth0
+
+You can influence driver mode by renaming the .xif file.
+recognized filenames:
+
+"FEC.XIF" => Auto-Negotiate, no promiscuous mode
+"FECP.XIF" => Auto-Negotiate, promiscuous mode
+"FECP10.XIF" => 10Mbit half duplex, promiscuous mode
+"FEC10.XIF" => 10Mbit half duplex, no promiscuous mode
+
+
+
+How it works
+============
+
+The core of this driver is the so called DMA cookie.
+This cookie provides us with pointers to the so called Multichannel
+DMA API. That API is provided by Freescale and built into FireTOS.
+Most FEC drivers (and also many others) are built on top of the
+MCDMA API. For more info read the "Multichannel DMA API User's Guide"
+and MCF5475 Reference Manual provided by Freescale.
+
+Currently nearly the same Network Buffer Scheme as FireTOS uses,
+is used for packet buffering. It makes use of the
+dma_malloc / dma_free functions provided with FireTOS DMA cookie.
+These functions work on memory areas which aren't affected
+by CPU cache. We could also use cache-visible memory,
+but then we would have to flush the cache (regions) before
+we send / receive data. Another Option is to use a static RAM
+area, but there isn't much space, which forces to use less
+buffer descriptors ( around 3 for rx, 3 for tx ) and that slows
+down transfer speeds alot. So the usage of SRAM is a bit
+problematic. (Altough SRAM access time is faster.)
+
+The DMA Cookie also provides us with the Freescale Multichannel
+DMA API + dma utility functions. With these functions we can
+start an so called "DMA task". There are specific DMA
+tasks for Receiving / Transmitting FEC data. It's built within the
+DMA API. So everything we have to do: start the dma task, and
+most of the work is done. The FEC is controlled by the DMA Task,
+and the driver just needs to handle incoming packets and submit
+outgoing packets to the task.
+
+While writing this, there is no official release of FireTOS which
+contains the DMA Cookie. So you either have to look for an
+non-official version, or wait until Didier Mequignon releases the
+next FireTOS version.
+
+Enjoy!
+
+m0n0
+
+7. Nov. 2011
diff -aurN -x CVS ./xif.orig//fec/SRCFILES ./xif/fec/SRCFILES
--- ./xif.orig//fec/SRCFILES 1970-01-01 01:00:00.000000000 +0100
+++ ./xif/fec/SRCFILES 2011-11-10 20:49:37.000000000 +0100
@@ -0,0 +1,19 @@
+# This file gets included by the Makefile in this directory to determine
+# the files that should go only into source distributions.
+
+FECDMA_SRCS = \
+ dma.c \
+ am79c874.c \
+ fec.c
+
+COMMON_SRCS = \
+ ../main.c
+
+HEADER = \
+
+
+COBJS = \
+ $(COMMON_SRCS) \
+ $(FECDMA_SRCS)
+
+SRCFILES = $(HEADER) $(COBJS)
diff -aurN -x CVS ./xif.orig//Makefile ./xif/Makefile
--- ./xif.orig//Makefile 2011-11-11 00:51:02.000000000 +0100
+++ ./xif/Makefile 2011-09-11 00:04:12.000000000 +0200
@@ -6,7 +6,7 @@
rieblspc rieblspc_fast rieblmst rieblmst_fast rieblste riebltt
SHELL = /bin/sh
-SUBDIRS = nfeth daynaport ethernat
+SUBDIRS = nfeth daynaport ethernat fec
srcdir = .
top_srcdir = ../..
Index: ./sys/cookie.h
===================================================================
RCS file: /mint/freemint/sys/cookie.h,v
retrieving revision 1.16
diff -a -u -r1.16 cookie.h
--- ./sys/cookie.h 2 Jun 2010 20:27:51 -0000 1.16
+++ ./sys/cookie.h 10 Nov 2011 21:53:56 -0000
@@ -73,6 +73,7 @@
# define COOKIE_RSVF 0x52535646L
# define COOKIE_FSEL 0x4653454CL
# define COOKIE_HBFS 0x48424653L /* BoxKite File Selector */
+# define COOKIE_DMAC 0x444D4143L /* FireTOS DMA API */
/* Not that we want to support these below ... */
# define COOKIE_STiK 0x5354694bL
@@ -83,8 +84,7 @@
# define COOKIE_CT60 0x43543630L
# define COOKIE_HADES 0x68616465L
-/* values of MCH cookie
- */
+/* values of MCH cookie */
# define ST 0
# define STE 0x00010000L
# define MEGASTE 0x00010010L